Hi NXP,
Please help me answer the following three questions.
1.I can't find the control register for reset monitor. I don't know how to turn on or off the reset monitoring function of POR_WDG. Please tell me the location of the register.
2. How does the reset monitoring function detect that the system is stuck in the reset sequence? Does it detect registers that have not been successfully reset?
3.The reset monitoring function indicates that after POR_WDG times out, the system deadlock position can be captured in DCM's DCMROPPn register. Can these states only let us know the system deadlock position after POR_WDG times out? Or is it the state of DCM's DCMROPPn register that determines the POR_WDG timeout?
Best regards,
Li 3.
Hi @li3,
1.
It can be disabled in DCF record programmed to UTEST.
S32K3xx RM, Chapter 37 Device Configuration Format (DCF) records
Refer to S32K3xx_DCF_clients.xlsx attached to the RM.
2 & 3.
The system goes through certain stages on the reset exit.
Figure 135. Functional reset flow
The DCM's DCMROPPn registers inform at what stage the WDOG overflowed.
Regards,
Daniel
Hi Daniel,
Thank you for your reply.
Please specify how to disable POR_WDG Reset monitoring?
I found the form, but I can't use it.
Best regards,
Li 3.
