S32K312 Cache

[PINKMAN]

Hello expert:

may I ask you a question? We know that the running speed of code varies in different types of memory, roughly from fastest to slowest as TCM > RAM > FLASH. By default, the code runs in FLASH. I can add the section attributes of TCM or RAM to function definitions and declarations to make the code run in the corresponding memory. However, I've noticed that the running speed in Cache is similar to that in TCM. Our project has already enabled the cache, but the cache size is only 8k, and its address is not visible. Is it impossible for users to set which code runs in the cache by themselves, and can we only enable or disable it? If it is possible to specify which regions are cacheable, how should I implement it?

[davidtosenovjan]

Pay attention to example code here:

https://community.nxp.com/t5/S32K-Knowledge-Base/Example-Siul2-Port-Ip-Example-S32K344-ITCM-DTCM-S32...

Note that Execution speed from cache is expected to be the same as for TCM.

[PINKMAN]

thanks for offer the demo for me, actually i know how to integrate ITCM and DTCM memory.

What I want to know is how to place functions or data in the cache for execution, or in other words, how to specify which part of the memory is cached and which part is not. In my project, the cache has been enabled, with both I-CACHE and D-CACHE being 8k each, but I don't know how to use them.

[davidtosenovjan · Accepted solution]

You have there defined memory segment int_sram_no_cacheable. You may use

__attribute__((section(".int_sram_no_cacheable"))) for those functions that are not supposed to be cached. Others are being cached by default.

You may also configure it by MPU for specific regions. You can also disable cache completely.