Hi@lua40927
1.Yes — if you configure multiple RX message buffers with the same acceptance criteria, FlexCAN does not simply overwrite MB0 immediately. With the normal matching behavior, it scans RX MBs from low number to high number, and if the first matching MB is not “free-to-receive,” it keeps looking for another matching MB that is free. So if MB0 already contains an unread matching frame, the next matching frame can be stored in MB1, then MB2, and so on, as long as those MBs are also matching and free. If no matching/free MB remains, FlexCAN overwrites the last matched MB and sets its CODE to OVERRUN .
2.No such info available.
I can give you some experience summaries and comparisons.
- If your priority is strict receive order + simpler draining logic , FIFO is better aligned to that use case because it is a true ordered queue with internal pointer handling.,
- If your priority is maximum buffering depth using many RX slots for Classic CAN traffic, dedicating many MBs to reception can give you much more room than the six-deep legacy FIFO, at the cost of more software management and possible reordering by timestamp.,,
- If you want DMA-based reception , the available S32K material says DMA is supported for RX FIFO, not MBs. Specifically, an S32K support answer states “DMA is supported only over RXFIFOs (legacy or enhanced) no over MBs.”
- On S32K312, Enhanced Rx FIFO is available only on FlexCAN0 and that legacy and enhanced FIFO cannot be enabled at the same time.
Note:
We recommend using your company email to register your NXP account, as general email addresses offer limited technical support.