S32K311 is reset when stop debug mode

[vanketnguyen]

Hi,

When we use debug mode, it works fine, but when we stop debug mode, then S32K311 got reset when at high frequency (120 Mhz), however it still works ok (S32K311 does not reset)  at low frequency (60 Mhz).

The setup is S32K31x EVB + S32SD v3.5 + RTD 3.0.0.

Our application needs to run at high frequency. Can you help to check what the root cause?

[vanketnguyen]

Hi,

Customer is able to solve the issue now after they set HSE clock at 60 Mhz

[vanketnguyen]

Hi Daniel,

We have configured all clocks according to the table 148 as you mentioned. We think the root cause seems like that when we write DIV bit of MUX_0_DC_2 register (MC_CGM.MUX_0_DC_2[DIV] ) with a value different from 1, then the reset happens.  There is one ticket as below, and @VaneB said it was due to the RTD 3.0.0. Could you help to check and confirm?

https://community.nxp.com/t5/S32K/S32K312EVB-reset-problem/m-p/1671141#M24067

To provide more detail, to avoid the system reset, we have to set MC_CGM.MUX_0_DC_2[DIV]=1, then AIPS_SLOW_CLK is out of range. To fix this, we have to reduce PHI0 (CORE PLL Output divider 0) from 120 Mhz to lower value , 60 Mhz.

[danielmartynek]

Hi @vanketnguyen,

I just sent you an email.

Regards,

Daniel

[danielmartynek]

Hi @vanketnguyen,

Can you read the MC_RGM[DES, FES] registers to identify the source of the reset?

Is the HSE_FW installed on the MCU?

Thank you,

BR, Daniel

[danielmartynek]

Hi @vanketnguyen,

I was able to reproduce the issue.

It works with the Power_Ip driver.

My test project is attached (RTD 3.0.0_P07_D2306).

Regards,

Daniel

[danielmartynek]

Hi @vanketnguyen,

Something similar was discussed here:

https://community.nxp.com/t5/S32K/The-program-runs-normally-with-a-debugger-but-the-program-runs/m-p...

Make sure that all the clocks are configured according to Table 148. Option B - Reduced Speed mode (CORE_CLK @ 120 MHz).

Regards,

Daniel