S32K3 Triggering SPI DMA from external trigger

[Rohitk23]

Hello!

I am currently trying to interface S32K344 with a 24-bit ADC ads130b04-q1 which is expected to run at its max data rate (~32kSPS), via the SPI interface.  This ADC features an active low data ready interrupt pin.

The way that I want it to work is that whenever the MCU detects a falling edge on the selected pin, the SPI DMA would immediately get triggered to send out the command to read the ADC DATA.

When such data (4 bytes) has been received, I would like to have it automatically stored.  I am assuming that the SPI DMA can also do that for me?  So in this case, I may need both the TX and RX channel DMA'ed.

That said, I cannot seem to find a good example linking this procedure mentioned.  May anyone please kindly point me to the correct example or examples?

NOTE: I'm using \SW32K3_S32M27x_RTD_R21-11_4.0.0_P01\eclipse\plugins\Spi_TS_T40D34M40I0R0\examples\EBT\S32K3XX\Spi_Transfer_S32K344

Thank you very much in advance!

[Rohitk23]

Hello Daniel,

I have done configuration as per example provided by you. But it seems after first initial transmit, all next jobs are reporting

SPI_E_SEQ_PENDING. Following is the main functions sequence I am currently using. I have also attached some screenshots of basic configuration. Could you please check and let me know if anything I am missing here?

Spi_SetAsyncMode(SPI_INTERRUPT_MODE);

Spi_WriteIB(SpiConf_SpiSequence_SpiSequence_isoadc, TxChBuf0);

Spi_AsyncTransmit(SpiConf_SpiSequence_SpiSequence_isoadc);

while (SPI_SEQ_OK != Spi_GetSequenceResult(SpiConf_SpiSequence_SpiSequence_isoadc));

Spi_ReadIB(SpiConf_SpiSequence_SpiSequence_isoadc, RxChBuf0);

[danielmartynek]

HI @Rohitk23,

Can you use Spi_GetStatus() instead of Spi_GetSequenceResult()?

Thank you

[Rohitk23]

Hello Daniel,
I tried using Spi_GetStatus() instead of Spi_GetSequenceResult() and it is always returning SPI_BUSY. What could be the reason.?

[danielmartynek]

Hi @Rohitk23,

Do you use the Host request (HREQ) already in the project?

I would recommend testing the SPI without HREQ first.

Can you monitor the bus with an oscilloscope?

If the HREQ is used, plase scope it too.

BR, Daniel

[Rohitk23]

Thanks. There was issue with interrupt, and it was disabled. I disabled HREQ. I could see SPI is running in async mode without DMA. But now I am trying to integrate SPI with DMA I see that SADDR and DADDR are correctly mapped but DADDR is not updating with provided data. I have attached log for the same. I have also configured DMA interrupts and enabled it during initialization. Could you please check logs and which can gives hints for what config i have done.

[Rohitk23]

Forgot to attach log file with last reply.

[danielmartynek]

Hi @Rohitk23,

Please check the DMAMUX too.

I don't see the registers in the log.

Thank you

[Rohitk23]

Yes, these are also captured. Please have a look on this as well. Please let me know if you find any incorrect configuration.  

[Rohitk23]

Hello Daniel,
Did you find any incorrect settings in the configuration. Is there anything i am missing in the configuration point of view.

[danielmartynek]

Hi @Rohitk23,

The only thing I have noticed is that there is an error on the source read in descriptor 0, that is the LPSPI1_TX.

Are the SRAM TX RX buffers protected my MPU/XRDC?

Also, you might not see the RX data in the buffer simply because the core read the data from the cache not the SRAM.

You can place the buffer in no_cacheable SRAM region:

#pragma GCC section bss ".mcal_bss_no_cacheable"
volatile uint32_t RX_buffer;
#pragma GCC section bss

Or use the Cache_Ip.h APIs to invalidate the cache.

Regards,

Daniel

[Rohitk23]

Hello Daniel,

The Tx/Rx buffers are not protected by MPU. Also, I tried with non-cacheable region for Tx/Rx buffers, but it's not worked. Is there any additional interrupts need to be enabled for the DMA transfer. Currently I have enabled interrupts for DMA TCD0 and DMA TCD1, interrupt sources 20 and 21 respectively. I have attached screenshots of DMA Interrupt configuration and SPI configuration with test code for the reference. Could you please have look on it.

[danielmartynek]

Hello @Rohitk23,

I see there is a new SPI DMA RTD Tresos project.

Can you compare the configuration?

Thank you

[Rohitk23]

Hello Daniel,

Thanks for the example. I have checked this and difference is its implemented with scatter gather configuration. I tried this implementation, but it seems same problem. I see Source address of TCD0 and Transmit buffer addresses are not matching. Also, ISR Spi_SeqNotification0 never get called.  I have attached logs of this example for your reference. Please let me know if you find any incorrect configuration. 

Thanks again.!

[danielmartynek]

Hello @Rohitk23,

I just notived that you use TCR as the destination address not TDR.

BR, Daniel

[Rohitk23]

Hello Daniel,

Thanks for reply and solution provided. I am trying to co-relate api's from your example with Autosar api's and trying to do the configuration in EB. Hope it would work. I'll update once it works.

Thanks Again! 

[danielmartynek]

Hi @Rohitk23,

There is this example you can refer to:

https://community.nxp.com/t5/S32K-Knowledge-Base/Example-S32K312-SPI-Transmit-amp-Receive-Using-DMA-...

I don't see any SPI DMA example built with RTD 4.0.0.

I don't know the specifics of this use case, but both the LPSPI module and the RTD driver supports Host request that can be used here:

More details in the RM.

Regards,

Daniel