S32K3 BCTU Issue

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NewbieNerd
Contributor IV

Hello, S32K3 Team,

We are currently experiencing an issue while configuring eMios-BCTU-ADC.

When executing Adc_EnableCtuControlMode, the process frequently halts at the Bctu_ConfigAndUpdateFifoNotification function. Although the notification configured in the FIFO occasionally gets triggered, in most cases, the system stops responding at this point.

We would appreciate your insight into the root cause of this issue, as well as any recommended solutions.

Please find our configuration attached below for your reference.

Best regards,

 

adcbctu6.pngadcbctu5.pngadcbctu4.pngadcbctu3.pngadcbctu2.pngadcbctu1.pngadcbctu0.png

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

it looks it has some result in FIFO1 at time of enabling its interrupts. If those are initialized before it would be OK, but I would expect commands come after all is initialized. Lets try to start eMIOS as final steps after all init is done.

BR, Petr

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

shared configuration looks normal, so hard to say what can be wrong, if other non listed setting or the code you have. For example be sure you enable HW trigger after all init is done, etc.
You can refer to below motor control solutions project which includes eMIOS-BCTU-ADC mechanism as well and contains high-level Autosar project too.
https://community.nxp.com/t5/S32K-Knowledge-Base/S32K3-Motor-control-SW-examples/ta-p/1804577
Good RTD low level examples are posted at https://community.nxp.com/t5/S32K-Knowledge-Base/RTD400-LLD-K344-ADC-SW-HW-trigger/ta-p/1966179.

BR, Petr

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NewbieNerd
Contributor IV

Thank you for your reply.

As you mentioned, I begin by initializing the peripheral modules in the following order:
Mcu → Port → Dio → Adc → Gpt → Mcl → Icu → Pwm,
and then I proceed to call the Adc_EnableCtuControlMode function.

To investigate whether the issue might be related to the operation of the eMIOS module in the MCL, I also tested invoking Adc_EnableCtuControlMode before calling the MCL initialization. However, in both cases, the behavior is inconsistent—the system mostly halts, and only occasionally does it operate successfully.

I would greatly appreciate your advice on this matter.

/* ADC */
Adc_Calibrate(AdcHwUnit_0, &CalibStatus_0);
Adc_Calibrate(AdcHwUnit_1, &CalibStatus_1);


if (CalibStatus_0.AdcUnitSelfTestStatus == E_NOT_OK && CalibStatus_1.AdcUnitSelfTestStatus == E_NOT_OK)
{
  return;
}

/* BCTU */
Adc_DisableCtuControlMode(AdcHwUnit_1);
Adc_EnableCtuControlMode(AdcHwUnit_1);
Adc_CtuEnableHwTrigger(AdcHwTrigger_0);


Adc_SetupResultBuffer(0U, s_usAdcReadBuffer_0);
Adc_EnableGroupNotification(0U);
Adc_StartGroupConversion(0U);
 

Best regards,
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PetrS
NXP TechSupport
NXP TechSupport

Hi,

if you share full simplified project, we can test on EVB.

BR, Petr

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NewbieNerd
Contributor IV

First of all, I apologize for the delayed response, and I kindly ask for your understanding that, due to company policy, I am unable to upload files.

The issue occurs within the Bctu_ConfigAndUpdateFifoNotification function, specifically in the following code segment:

Mask |= FifoConfig->FifoDmaEnable ? (BCTU_FIFOCR_DMA_EN_FIFO1_MASK << FifoConfig->FifoIndex) : 0U;
Mask |= FifoConfig->bEnNotif ? (BCTU_FIFOCR_IEN_FIFO1_MASK << FifoConfig->FifoIndex) : 0U;
SchM_Enter_Adc_ADC_EXCLUSIVE_AREA_65();
BctuBasePtr->FIFOCR &= ~(Mask);
BctuBasePtr->FIFOCR |= Mask;
SchM_Exit_Adc_ADC_EXCLUSIVE_AREA_65();


After this code is executed, the system no longer proceeds. It seems to get stuck or halt at this point.

I would greatly appreciate your assistance in identifying the cause of this issue and any potential resolutions.


There are rare cases where the execution succeeds, so I am wondering if there are specific conditions that must be met when setting the FIFOCR register.

In normal operation, the value of the FIFO1DR register changes.

(picture adc0 <-> adc1)

In abnormal operation, it does not.

(only adc1)

Thank you for your continued support.

Best regards,

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

it looks it has some result in FIFO1 at time of enabling its interrupts. If those are initialized before it would be OK, but I would expect commands come after all is initialized. Lets try to start eMIOS as final steps after all init is done.

BR, Petr

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