S32K148 FlexCAN1 Interrupts Going to DefaultISR Despite Proper Vector Table Registration - FreeRTOS

[elb1]

Vector Table Setup:

Vector table is copied from Flash to RAM during startup via startup_S32K148.S
__VECTOR_RAM is properly set at 0x1FFF8000
S32_SCB->VTOR correctly points to RAM vector table
Assertion e_assert_void((uint32_t)__VECTOR_RAM == S32_SCB->VTOR) passes

Interrupt Registration:

Using intc_register_handler(CAN1_ORed_0_15_MB_IRQn, CAN1_ORed_0_15_MB_IRQHandler, NULL)
Handler address is correctly written to __VECTOR_RAM[104] (IRQ 88 + 16 = vector 104)
intc_set_priority(CAN1_ORed_0_15_MB_IRQn, 17) sets priority to 17
intc_enable_irq(CAN1_ORed_0_15_MB_IRQn) enables the interrupt in NVIC

FlexCAN1 Configuration:

Mailbox Count: 32 mailboxes configured (FEATURE_CAN1_MAX_MB_NUM = 32U)
Active Mailboxes: IMASK1 register shows value 0x00000600
Interrupt Grouping: Using CAN1_ORed_0_15_MB_IRQn which should handle mailboxes 0-15

FreeRTOS Configuration:

configMAX_SYSCALL_INTERRUPT_PRIORITY = 16
configPRIO_BITS = 4
Using BASEPRI-based interrupt masking
NVIC priority grouping set to 0: S32_SCB->AIRCR = 0x05FA0000 | (0 <<

What I've Verified:

Vector Table Integrity: Debugger confirms __VECTOR_RAM[104] contains correct handler address
NVIC Configuration: NVIC->ISER[2] & (1 << 24) shows IRQ 88 is enabled
Priority Settings: NVIC->IP[88] = 17 confirms priority is set
Interrupt Generation: FlexCAN1 hardware is generating interrupts (IFLAG1 = 0xF0000200)
Handler Function: CAN1_ORed_0_15_MB_IRQHandler exists and is properly linked

Investigation Results:

When CAN interrupt fires, execution goes to DefaultISR instead of the registered handler
No hardfault or other exception occurs
Multiple different approaches tried (direct vector manipulation, priority adjustments, etc.)
Issue persists regardless of interrupt priority level (tested 5, 17, 20)

[elb1]

One thing that i wanted to add is that i am also having fifo enabled, because i am trying to fifo CAN for UDS and normal MBs CAN with interrupts for application messages, and with my current implementation the UDS is working as it should (fifo) but the app messages whwnever they are received default handler will hit even if all registers are correct, can this affect ?

[PetrS]

Hi,

RXFIFO interrupts invokes CAN1_ORed_0_15_MB_IRQn as well, so if this is working for message coming to RXFIFO, it should work for rest of regular MBs as well.

BR, Petr

[elb1]

In my case, FIFO doesn't actually use interrupts (it polls), but for regular mailboxes i want to use the interrupts.

thank you

[PetrS]

Hi,

if you cannot share simplified project, then please specify the S32DS and driver version(none, SDK,RTD) you use, so I can try to replicate behavior.

BR, Petr

[elb1]

It worked now when i commented this line in my linker file 

/* SRAM_L */ 
/* m_session (RW) : ORIGIN = 0x1FFE0000, LENGTH = 0x00000080 */
m_data (RW) : ORIGIN = 0x1FFE0080, LENGTH = 0x0001FF80

Even though i checked VTOR in debug mode and it was pointing to 0x1FFE0080, i suppose it should work but it didn't, do you have any clue why it didn't work
Thank you

[PetrS · Accepted solution]

Hi,

the Vector table must be naturally aligned to a power of two whose alignment value is greater than or equal to (Number of Exceptions supported x 4). In the case of a vector table with 170-180 vectors the next power of two is 256 and converting that from words to bytes give a byte alignment of 1024.

BR, Petr

[elb1]

I added this code and when i send message to the mcu it will come to this function and the value of "g_active_vector" is "104"

void DefaultISR(void)
{
/* Capture the active vector number from SCB->ICSR register */
g_active_vector = (S32_SCB->ICSR & S32_SCB_ICSR_VECTACTIVE_MASK) >> S32_SCB_ICSR_VECTACTIVE_SHIFT;

while (1)
{
__asm("nop");
}
}

I also inspected SCB and NVIC registers, when the program jump to default isr:
SCB->ICSR -> 0x0440F868

For the NVIC register ISER, ICER you can see the capture attached and for the IP they are all set to 0x00 except NVICIP88 NVICIP89 they are both equal to 0x50

[PetrS]

Hi,

my guess is that either SCB->VTOR or vector table offset 0x1A0 does not have expected values. But you already checked that.
Can you share simplified project showing issue?

BR, Petr

[PetrS]

Hi,

hard to suggest more, the vector table and interrupt configuration appear correct.
Do you use other interrupts as well, like from PIT, and those are hit properly?

You can try to modify DefaultISR to capture the active vector number. SCB->ICSR gives you the currently active interrupt number (VECTACTIVE field) 

void DefaultISR(void)
{
    uint32_t active_vector = (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) >> SCB_ICSR_VECTACTIVE_Pos;
    while (1); // Breakpoint here to inspect 'active_vector'
}

Or set a breakpoint in DefaultISR and inspect SCB->ICSR, NVIC registers (ISER, ICER, IPR, etc.), Vector table contents at runtime.

Also you can temporarily assign unique dummy handlers to each IRQ to see which one is triggered.

BR, Petr