I'm having an issue where I'm getting a bus fault after enabling the LPIT0 ISR. The timing of the issue is not consistent: sometimes I'll run for a second or two, sometimes I'll run for 10+ seconds. Using a modified version of the AN12218 Bootloader.
Debugger shows my LPIT0_Ch0_IRQHandler called, then another signal handler called for the default handler (I'm guessing it's the Hard Fault Handler)
S32 Design Studio for ARM reports the following on the console:
BusFault: A bus fault has occurred during instruction prefetching.
CFSR is 0x00000100
HFSR is 0x40000000
I'm enabling it using the following code similar to the code used in the AN5413 S32K1xx Series Cookbook section 2.3:
/* set up interrupt handling for the timer */
S32_NVIC->ICPR[1] = 1 << (48 % 32); /* IRQ48-LPIT0 ch0: clr any pending IRQ*/
S32_NVIC->ISER[1] = 1 << (48 % 32); /* IRQ48-LPIT0 ch0: enable IRQ */
S32_NVIC->IP[48] =0x0A; /* IRQ48-LPIT0 ch0: priority 10 of 0-15*/
/* Enable bus clock to PIT */
PCC->PCCn[PCC_LPIT_INDEX] = PCC_PCCn_PCS(3) | PCC_PCCn_CGC_MASK; /* Clock src=3 (FIRC_DIV2_CLK)*/
/* Turn on PIT */
LPIT0->MCR |= LPIT_MCR_M_CEN_MASK; /* enable module clock */
LPIT0->MIER = 0x00000001; /* TIE0=1: Timer Interrupt Enabled for Chan 0 */
/* Configure Channel 0 to trigger as defined in pit.h */
LPIT0->TMR[0].TVAL = TRIG_PERIOD;
/* Enable timer */
LPIT0->TMR[0].TCTRL = LPIT_TMR_TCTRL_T_EN_MASK;
ISR Code is:
void LPIT0_Ch0_IRQHandler (void) {
if(LPIT0->MSR & LPIT_MSR_TIF0_MASK){
LPIT0->MSR |= LPIT_MSR_TIF0_MASK; /* Clear LPIT0 timer flag 0 */
is_triggered = 1;
}
}
is_triggered is a volatile int that's only accessed from one function in the regular code which is not in the call chain when the fault occurs (access has a disable interrupts and put a dsb & isb after disabling interrupts)
When it happens I'm performing a Flash Command Sequence in fsl_flash_driver_c90tfs.c (Copyright 2016), but that's the main thing that the bootloader is doing.
