S32K116 & voltage supervisor

[Pete66]

Reviewing the hardware engineers schematic & there is not a voltage supervisor connected to nRESET. My experience has been that you always have a supervisor. Is a voltage supervisor; (1) Not needed, (2) Recommended, (3) Needed?

PS Where is the S32K116 EVB schematic? I wanted to check what the reference design did.

Regards

[Pete66]

Thanks. I understand that the ramp must be only up and within limits. The BD wont do that. What confuses me is that the S32K1xx will have decoupling. So if the PSU flips out for a small time then you could have a /\/ ramp. Does the SBC also enforce a minimum off period or have I been out in the sun too long? We have used LMZM23600V5SILR but have not connected PGOOD to nRESET. What do you think, should we rework?

[Robin_Shen]

Do you mean you can see the voltage output from LMZM23600V5SILR show below(Not Correct red circle)?

MCU power supply ramp rate.png

[Pete66]

Thanks.

EDIT: I cut and pasted LMZM23600V5SILR instead of UJA1169. I have corrected.

Almost. What I mean is that the UJA1169 might be perfect and output the first 'CORRECT' ramp. If the input to the UJA1169 is bad then the UJA1169 must switch off however.

This on/off might have the end effect of producing the output you circle at the Vdd input of the NXP MCU. The UJA1169 behaves correctly, positive ramp or 0V but the MCU circuit is an RC (with decoupling).

That leaves me wondering about the NXP statement 'or damage in the MCU'. Perhaps the incorrect ramp has to exist for a long time before damage?

[Robin_Shen]

Hi Pete66,

You can download the S32K116EVB Evaluation Board – Schematics from S32K116 Evaluation Boards for General Purpose.
Would you please let me know what kind of voltage supervisor do you need?
The on board SBC UJA1169TK/F will monitor the voltage.

UJA1169TK.png

Best Regards,
Robin
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[Pete66]

Thanks.

I did not know that there were different types of voltage supervisor.

My experience is that people generally use something like the BD45271G to hold the CPU in reset whilst the power supply ramps up.

Section 3.2 of AN5426 revision D states that the PSU must have a fast enough 'ramp time' or this might result in 'stuck operation' etc.

(1) I assume therefore that we must either (a) have a fast rise PSU OR (b) if we cannot guarantee PSU ramp use a BD45271G  or similar?

(2) That the S32K116 will not be damaged by a slow PSU ramp provided that the NXP is held in RESET until voltage is good?

Regards

[Robin_Shen]

The reset should not be high before VDD.
The power on ramp rate must be always meet during the entire power on sequence.

SBC can meet the above two conditions at the same time.
BD45271G can only ensure that Reset is later than VDD high.