S32K Can Filtering

cancel
Showing results for 
Search instead for 
Did you mean: 

S32K Can Filtering

Jump to solution
1,644 Views
NXP Employee
NXP Employee

Im trying to help a customer come up with the best way to do CAN filtering but S32K documentation is confusing about how to setup the mask and the individual filter elements. Can you tell us how should we set up the filter for the following scenario?

 

For our scenario, RX FIFO is enabled. We have messages coming to CAN1 with the messages IDs ranging from 0x402-0x450. We would like to allow all

the messages to pass except for two messages: 0x44d and 0x44e.

 

Can you show us one way to set up the masks and the individual filters to be able to do this?  I see the CAN_SetRxFilter function but we have examples.  I just want to make sure I set this up most efficiently and dont spin many cycles.

 

1 Solution
540 Views
NXP TechSupport
NXP TechSupport

Hi Daniel,

see main.c I sent for FORMAT A utilization. It uses ID table suggestion I mentioned in my first reply.

The same ID/mask proposal can be reused for FORMAT B too and so number of filter elements can be reduced to half.

However SDK function FLEXCAN_DRV_SetRxIndividualMask is not able to set different mask for RXIDB_0/RXIDB_1 identifiers, so ID ranges cannot be used easily. Unless you will write directly to RXIMRx with right value.

BR, Petr 

View solution in original post

0 Kudos
13 Replies
540 Views
NXP Employee
NXP Employee

Hello Daniel,

I have looked over your case and based on the scenario you presented you need about 80 filters this can be done useing filter type B and 40 filters this configuration will require all 16 Mbs available for CAN1 instance on S32K144 for RxFIFO, no other MB will be available for other operation.

Here is the driver PEX configuration

pastedImage_1.png

Here you have an example that will config the filters and then initialize the Driver.

void FlexCANInit(void)
{
flexcan_id_table_t idtable[80];
uint16_t id=2;
for (;id<0x50;id++)
{
if ((id == 0x4d) || (id == 0x4e))
{
idtable[id-2].id = 0x44f;
idtable[id-2].isExtendedFrame = false;
idtable[id-2].isRemoteFrame = false;
}
else
{
idtable[id-2].id = (0x400+id);
idtable[id-2].isExtendedFrame = false;
idtable[id-2].isRemoteFrame = false;
}
}
for(;id<80;id++)
{
idtable[id-2].id = 0x44f;
idtable[id-2].isExtendedFrame = false;
idtable[id-2].isRemoteFrame = false;
}

/*
* Initialize FlexCAN driver
* - 8 byte payload size
* - FD enabled
* - Bus clock as peripheral engine clock
*/
FLEXCAN_DRV_Init(INST_CANCOM1, &canCom1_State, &canCom1_InitConfig0);
FLEXCAN_DRV_SetRxMaskType(INST_CANCOM1,FLEXCAN_RX_MASK_GLOBAL);
FLEXCAN_DRV_ConfigRxFifo(INST_CANCOM1,FLEXCAN_RX_FIFO_ID_FORMAT_B,&idtable[0]);
}

The read can be done from RXFIFO of received messages that will match between 0x402-0x450 without 0x44e and 0x44d.

BR,

Alexandru Nan

0 Kudos
540 Views
NXP Employee
NXP Employee
  1. When I set CAN_MCR[IRQ] to 1 (individual MASK) and set the filter table elements according to Petr’s suggestion, I see that everything

    Passes through.

  • I tried a simple scenario with just one filter element of 0x402 and RXIMR[0]= 0x7ff. In this scenario I expect that only 0x402 passes

Through. But I see everything passing. Is there something I am missing?  Is it possible for you to provide a code snippet of the solution that you suggested.

 

  1. When I set CAN_MCR[IRQ]  to global MASK according to Alexandru’s suggestion, the solution works up to 40 filters but beyond that I would

Run out of RAM. So this solution alone would not work for me except if I can find a way to define individual masks.

 

0 Kudos
540 Views
NXP Employee
NXP Employee

Regards the first question how many filters did you configured ?!

If you configured more filters than peter suggested CTRL2[RFFN]=1 and you didn't configured all affected RXIMR and the maybe Global MAsk if other filters are affected by then if one filter remain set to 0 then this means accept all IDs. 

0 Kudos
540 Views
NXP Employee
NXP Employee

So I tried this scenario:

1. Configured CTRL2[RFFN]= 1 which according to reference manual means number of RX FIFO filter elements are 16. And defined the filter values as following, all 0x402:

2. static const uint32_tfc_filter_value[16]={

3. 0x402,0x402,0x402,0x402,0x402,0x402,0x402,0x402,0x402,0x402,0x402,0x402,0x402,0x402,0x402,0x402

4.

5. };

1. Set the CAN_MCR[IRQ] to 1 so that elements in ID table are affected by individual mask.

2. Set the global mask to 0xFFFF

3. Set the RXIMR values 0-16 to 0x7ff.

According to reference manual (page 569) this means that RX FIFO elements 0-9 will be affected by RX individual masks and the rest will be affected by RX FIFO global mask.

What I see is that for this simple example, still everything from 0x402 – 0x450 goes through. Whereas it should only allow 0x402. Can you tell me if there is something that I am not doing right here?

SENT FROM PHONE

Daniel Wax | Field Applications Engineer Automotive

NXP Semiconductors

411 E Plumeria Dr

San Jose, CA 95134

office: 408-518-5533

mobile: 408-981-9220

daniel.wax@nxp.com<mailto:daniel.wax@nxp.com>

All types of technical support (Schematic review, layout review, software review, hardware board and software) provided

by NXP Field application team are subject to NXP's general Terms and Conditions unless superseded by a direct contract.

The information contained in this message is confidential and may be legally privileged. The message is intended solely for the addressee(s). If you are not the intended recipient, you are hereby notified that any use, dissemination, or reproduction is strictly prohibited and may be unlawful. If you are not the intended recipient, please contact the sender by return e-mail and destroy all copies of the original message.

Unless otherwise recorded in a written agreement, all sales transactions by NXP Semiconductors are subject to our general terms and conditions of commercial sale<http://www.nxp.com/about/our-terms-and-conditions-of-commercial-sale:TERMSCONDITIONSSALE?fsrch=1&sr=1&pageNum=1>.

0 Kudos
540 Views
NXP TechSupport
NXP TechSupport

Daniel,

check using debugger if ID within ID filter table and mask in Mask registers is properly shifted according to IDE bit.

For standard IDs the ID and mask is shifted left by 19 bits, for extended IDs the IDE is set and the ID and mask is shifted left by 1 bit.

BR, Petr 

0 Kudos
540 Views
NXP Employee
NXP Employee

Any new ideas here?  Nothing has worked yet

0 Kudos
540 Views
NXP TechSupport
NXP TechSupport

Hi Daniel,

I have tested the filtering based on below example I did some time ago.

https://community.nxp.com/docs/DOC-343091

Attached is the main.c file you should use to implement ID table I proposed. Using this code the RXFIFO accepts only standard IDs in range 0x402-0x450 except of IDs 0x44D and 0x44D.

I found one mistake in my proposal; mask for ID element 3 should be set to 0x7F8 instead of 0x7F0.

Also bit 30 in mask register must be set so IDE bit checked, otherwise also some extended IDs will be accepted

Similar should be valid for bit 31 masking RTR.

Thus I used below code to set the mask registers properly.

uint16_t IDmask[10] = {0x7FF,0x7FF,0x7FC,0x7F8,0x7F0,0x7F0,0x7F0,0x7F8,0x7FF,0x7FF};

/* set individual masking type */
FLEXCAN_DRV_SetRxMaskType(INST_CANCOM1, FLEXCAN_RX_MASK_INDIVIDUAL);
for(id_counter=0;id_counter<10;id_counter++)
FLEXCAN_DRV_SetRxIndividualMask(INST_CANCOM1, FLEXCAN_MSG_ID_STD, id_counter, 0xC0000000|IDmask[id_counter]);
/* rest of filter items are masked with RXFGMASK */
FLEXCAN_DRV_SetRxFifoGlobalMask(INST_CANCOM1, FLEXCAN_MSG_ID_STD, 0xC0000000|0x7FF); 

BR, Petr

0 Kudos
540 Views
NXP Employee
NXP Employee

Petr

Thanks you, this is very helpful. For the customer’s case do you have a recommendation on Format A or Format B filtering type?

Daniel Wax | Field Applications Engineer Automotive

NXP Semiconductors

411 E Plumeria Dr

San Jose, CA 95134

office: 408-518-5533

mobile: 408-981-9220

daniel.wax@nxp.com<mailto:daniel.wax@nxp.com>

All types of technical support (Schematic review, layout review, software review, hardware board and software) provided

by NXP Field application team are subject to NXP's general Terms and Conditions unless superseded by a direct contract.

The information contained in this message is confidential and may be legally privileged. The message is intended solely for the addressee(s). If you are not the intended recipient, you are hereby notified that any use, dissemination, or reproduction is strictly prohibited and may be unlawful. If you are not the intended recipient, please contact the sender by return e-mail and destroy all copies of the original message.

Unless otherwise recorded in a written agreement, all sales transactions by NXP Semiconductors are subject to our general terms and conditions of commercial sale<http://www.nxp.com/about/our-terms-and-conditions-of-commercial-sale:TERMSCONDITIONSSALE?fsrch=1&sr=1&pageNum=1>.

0 Kudos
541 Views
NXP TechSupport
NXP TechSupport

Hi Daniel,

see main.c I sent for FORMAT A utilization. It uses ID table suggestion I mentioned in my first reply.

The same ID/mask proposal can be reused for FORMAT B too and so number of filter elements can be reduced to half.

However SDK function FLEXCAN_DRV_SetRxIndividualMask is not able to set different mask for RXIDB_0/RXIDB_1 identifiers, so ID ranges cannot be used easily. Unless you will write directly to RXIMRx with right value.

BR, Petr 

View solution in original post

0 Kudos
540 Views
NXP Employee
NXP Employee

Hello Daniel,

Be aware to the mentioned solution from Petr Stancik, setting individual mask register directly will require setting the the flexcan module in freeze mode. The SDK don't provide no public api for setting freeze mode.

0 Kudos
540 Views
NXP Employee
NXP Employee

Checked the debugger, and confirmed that as stated in the reference manual for format B, there are two standard IDs per register starting at bit 3 and 19 respectively.

The Mask registers are not readable by the debugger as they are only accessible in the freeze mode. But I tried copying both the right value and the shifted value to see if it makes any difference but it did not.

SENT FROM PHONE

Daniel Wax | Field Applications Engineer Automotive

NXP Semiconductors

411 E Plumeria Dr

San Jose, CA 95134

office: 408-518-5533

mobile: 408-981-9220

daniel.wax@nxp.com<mailto:daniel.wax@nxp.com>

All types of technical support (Schematic review, layout review, software review, hardware board and software) provided

by NXP Field application team are subject to NXP's general Terms and Conditions unless superseded by a direct contract.

The information contained in this message is confidential and may be legally privileged. The message is intended solely for the addressee(s). If you are not the intended recipient, you are hereby notified that any use, dissemination, or reproduction is strictly prohibited and may be unlawful. If you are not the intended recipient, please contact the sender by return e-mail and destroy all copies of the original message.

Unless otherwise recorded in a written agreement, all sales transactions by NXP Semiconductors are subject to our general terms and conditions of commercial sale<http://www.nxp.com/about/our-terms-and-conditions-of-commercial-sale:TERMSCONDITIONSSALE?fsrch=1&sr=1&pageNum=1>.

0 Kudos
540 Views
NXP TechSupport
NXP TechSupport

Hi Daniel,

Do you use standard or extended IDs?

Do you use latest SDK? Or do you have non-SDK code? 

BR, Petr

0 Kudos
540 Views
NXP TechSupport
NXP TechSupport

Hi Daniel,

The CAN_MCR[IRMQ] bit determines which mask register is used for the RXFIFO ID table elements. If CAN_MCR[IRMQ]=0 then all ID Table is affected by RXFGMASK. If CAN_MCR[IRMQ]=1, elements in ID table are affected by Individual Mask Registers (RXIMRx) according setting of CTRL2[RFFN].

There is bit2bit correspondence between received ID, mask and programmed MB ID or ID Table element. The mask says if corresponding incoming ID bit is compared with programmed ID bit.

If mask bit is cleared the incoming ID bit is not compared, it is don’t care. If mask bit is set, then there must be exact match between incoming ID bit and programmed ID bit. To receive a message into a MB/RXFIFO all bits with mask bit set must be equal to programmed one.

So assuming the above, mix of dedicated ID and ID ranges should be used within ID table. Below config can be used assuming CTRL2[RFFN]=1.

pastedImage_1.png

BR, Petr