Reset Generator question

[Febins]

Hi there, I am trying to answer some question from my company, cannot seem to find the answer for it. We are using S32K118 .

question 1) 

What is the highest voltage that the reset generator tracks Vcc before becoming active (e.g. reset follows the Vcc rail until Vcc reaches 1V)?

question 2) Is the reset generator slew rate dependent (see figure in 3.2.105 above dv/dt)?  

It would be really helpful if someone can answer this,

thanks

[danielmartynek · Accepted solution]

Hi @Febins,

1.

Out of the power-on reset, the MCU (its PN junctions) is not biased.

So, the reset module cannot control the reset_b until the VDD voltage reaches the forward bias voltage.

Once it can control the reset_b, the pin is asserted and stays asserted until the VDD LVR deassert level is reached.

2.

The ramp rate simply follows the VDD voltage.

Regards,

Daniel

[Febins]

1. Can you tell me what is the voltage value of VDD LVR deasset level? thanks

[danielmartynek]

Hi @Febins,

There is the assert threshold and its hysteresis specified in the DS.

BR, Daniel