RDBESSK358BMU Ethernet configuration

[gferretts]

I'm currently working on RDBESSK358BMU from NXP, the board has S32K358 with GMAC connected to Marvell Alaska 88e1510 transceiver and a eth gigabit port (HW scheme attached).

I'm wondering if i can use tcpip stack with lwip_baremetal examples with this configuration.

The example with Gmac_Loopback works, butlwip_baremetal_example fails on Gmac_initDMA like i saw in other posts it is a clock reference problem, but the board i'm using has an external clock on it, so i don't understand how to adapt the example to my hardware. Can someone give help? Thanks!

 

[PavelL · Accepted solution]

Hello @gferretts ,

I apologize for delayed reply.

Unfortunately, RD-BESSK358BMU is not in  my possession, so I'm not able to adapt lwip example for you. Anyway, I adapted lwip example for S32K358EVB-Q289, RGMII 100Mbps without any issues. Let me share basic steps I use for adoption (please note that some details might be related to S32K3 RTD / TCPIP version):

• Config Tool - Pins
  • Adopting pins to fit board's wiring
  • Set Slew rate as Fastest settings, if applicable
  • TX_CLK should be output for RGMII
• Config Tool - Clocks
  • GMAC clocks should look like that (note for GMAC 1Gbps: 25MHz -> 125MHz ; 50MHz -> 250MHz)

• Config Tool - GMAC driver
  • ETH_MAC_LAYE_TYPE_XGMII, REDUCED, set correct speed ETH_MAC_LAYER_SPEED_xxx
• Source code - device.c
  • Add RTD workaround as the very first rows of device_init()

/* Set RGMII mode configuration for GMAC0 in DCM module */
IP_DCM_GPR->DCMRWF1 |= DCM_GPR_DCMRWF1_MAC_CONF_SEL(0x01) | DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN_MASK;
/* Set RGMII RX_CLK arrives directly from the RX_CLK pin for GMAC in DCM module */
IP_DCM_GPR->DCMRWF3 |= DCM_GPR_DCMRWF3_MAC_RX_CLK_MUX_BYPASS(0x01);

• Source code - test.c
  • Alternatively, comment out section which shuts down TCP/IP stack after some time

This was the easier part.

Looking to schematic, you need to define GPIO PTC1 to provide valid reset pulse signal to the PHY and wait for a while before initializing GMAC. PHY usually works independently, in unmanaged mode, just configured by pin strapping. Sometimes, PHY requires management via SMI.

What S32K3 RTD version and what TCP/IP stack version do you use?

Best regards,

Pavel

[gferretts]

Hi @PavelL , thanks for your reply. I'm still having problems with lwip, i also have s32k3x8evb-q289 but i don't have a TJA daughter board so i need to test Ethernet on my S32K358BMU.

I'm using RTD3.0.0 with "TCPIP STACK 1.0.3 D2306", i attach my .mex config file where i tryied to replicate what you showed (clock configuration, GMAC pheripheral and pinout) and "device.c" with ETH_RESET from pin.

I tryied also to replicate your RTD turnaround manually since my rtd has no loopback define:

void device_init(void) {

uint16 pitPeriod;

/* Set RMII configuration for EMAC in DCM module */

//IP_DCM_GPR->DCMRWF1 = (IP_DCM_GPR->DCMRWF1 & ~DCM_GPR_DCMRWF1_EMAC_CONF_SEL_MASK) | DCM_GPR_DCMRWF1_EMAC_CONF_SEL(1U);

/* Manual RTD turnaround */

IP_DCM_GPR->DCMRWF1 = 0x80000040;

IP_DCM_GPR->DCMRWF3 = 0x2000;

....}

With this configuration, the example is able to achieve Gmac_Ip_InitDMA without Timeout and reaches mainloop, but pinging 192.168.0.200 from my Pc results in not reachable host and ping timeout. 

With oscilloscope i verified RXC is present (25MHz when Phy negotiates 100Mbps or 125MHz when 1Gbps) so there is some traffic coming from ETH port. Meanwhile on TXC now i see 125MHz too but TXD0,1 are never triggered.

I hope you can find what is happening wrong here. 

[gferretts]

Thank you very much @PavelL! I noticed i still had 100m as GMAC speed, by setting it to 1G to match 125MHz clock now it works fine with ping and TCP echo on port 7!

I also commented "Eth_T_InitPhys();" since my PHY was not in the phy list and it is configured via straps.

 

 

[PavelL]

Hello @gferretts ,

yes, that's what I have found. You were faster.

You may copy missing definition from RTD 5.0.0:
#define DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN_MASK (0x80000000U)
#define DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN_SHIFT (31U)
#define DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN_WIDTH (1U)
#define DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN(x) (((uint32_t)(((uint32_t)(x)) << DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN_SHIFT)) & DCM_GPR_DCMRWF1_MAC_TX_RMII_CLK_LPBCK_EN_MASK)

... just notice that the RTD workaround uses |= 

Regarding Eth_T_InitPhys() - yes, that was also right mode - this routine deserves a deep inspection.

Best regards,

Pavel