Possible H/W error in s32k148 flexcan controller

[freddy_ben-zeev]

I'm running an evaluation with CAN configured for FD at 1Mbps for arbitration phase and 2Mbps data phase. I'm generating traffic from PCAN-View on a PCN-USB X6 with 16 bytes data at 1msec intervals (at this rate some messages are dropped). Inside the IRQ handler it reads from the mailbox a DLC of 0 instead of 0xA, which I caught by adding an assert at that point. If during the assert I look at the MB register again it contains a correct value of 0xA.

Looks like the interrupt happens before the mailbox is up to date.

[freddy_ben-zeev · Accepted solution]

Thanks Petr & Alexandru. It does seem to be software related. Looks like the SDK driver for the flexcan does not do what Alexandru suggests above... The messages arrive asynchronously and if one arrives before the read is started it is not cleared by the read operation. I've solved it by clearing the MB read IRQ flag before enabling the new read interrupt.

[1515190497]

Coud you tell me how to clear MB?

[freddy_ben-zeev]

In a couple of places I'm clearing the MB read IRQ flag (inside the flexcan_driver.c file in the SDK) by calling the function FLEXCAN_ClearMsgBuffIntStatusFlag before the call to FLEXCAN_SetMsgBuffIntCmd (that enables MB IRQ). I use a critical section around both calls.

[PetrS]

Hi Freddy,

I am not aware of such HW error in FlexCAN module. It rather points to wrong SW handling as Alexandru wrote.

BR, Petr

[alexandrunan]

Hello, did you use SDK for this issue ?

Second when you read the mb content before did it you check the busy bit from Code Status of the mb ? In case that flag is still asserted then the content of MB is incoherent ! But be aware polling Code and Status Word of the MB will lock the mb in some cases like Code FULL or OVERRUN which will prevent writing another message in the MB.