Does it need to disable cache when write/erase PFLASH, DFLASH for S32k146 project.

[assangeye]

Hi,

At present I work on write to PFLASH and DFLASH memory. Im little confused about disabling flash cache.

There is flash partitioning example in S32SDK_S32K14x_EAR_0.8.6 where is code disabling flash cache:

/* Disable cache to ensure that all flash operations will take effect instantly, * this is device dependent */

#ifdef S32K144_SERIES

MSCM->OCMDR[0u] |= MSCM_OCMDR_OCM0(0xFu) | MSCM_OCMDR_OCM1(0xFu) | MSCM_OCMDR_OCM2(0xFu);

MSCM->OCMDR[1u] |= MSCM_OCMDR_OCM0(0xFu) | MSCM_OCMDR_OCM1(0xFu) | MSCM_OCMDR_OCM2(0xFu);

MSCM->OCMDR[2u] |= MSCM_OCMDR_OCM0(0xFu) | MSCM_OCMDR_OCM1(0xFu) | MSCM_OCMDR_OCM2(0xFu);

MSCM->OCMDR[3u] |= MSCM_OCMDR_OCM0(0xFu) | MSCM_OCMDR_OCM1(0xFu) | MSCM_OCMDR_OCM2(0xFu);

#endif /* S32K144_SERIES */

But in S32K-RM rev. 6 theres no bits OCM0, OCM2 for registers OCMDR[0], OCMDR[1] and any OCMx bits in OCMDr[2] and even register OCMDR[3]. OCM1 is 2bits wide, not 4bits like in axample above. Some of bits which is write in example is Reserved based on S32K-RM.

I think this code should look like this for S32K146:

S32K14x_RTM_SDK_V2.0.0

#ifdef S32K146_SERIES

MSCM->OCMDR[0u] |= MSCM_OCMDR_OCM1(0x3u);

MSCM->OCMDR[1u] |= MSCM_OCMDR_OCM1(0x3u);

#endif /* S32K146_SERIES */

Please clarify how to disable cache for memories for S32K146. What are advandages/disadvantages for disabling cache when write/erase PFLASH, DFLASH .

And i wonder to know  it is necessary to disable cache when write/erase PFLASH, DFLASH .Because i found that if this code existed in my project ,the time of executing every line of code will be slow.when i use IAR compier.

Now , In my project I dont use this code,and it can write and erase PFLASHorDFLASH as usual . Does it OK or these may be a bug?

Regards, Kai

[victorjimenez]

Hi Kai,

I recommend you to use the newest version of the SDK for the S32K146, S32K1xx RTM SDK v3.0.0.

Please check the following community post (link) to see how to disable the cache. Disabling the cache is not explicitly required but recommended, this is on the user's responsibility. You could refer to AN4745 (link) Optimizing Performance on Kinetis K-series MCUs.

Have a great day,
TIC

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