Channels CH1 and CH3 of PIT1 are utilized in my project: CH1 serves as the Wdg_ChannelTrigger for K344 with an interrupt cycle of 125ms, while CH3 is set for 10ms interrupt requests. A watchdog reset event occurred during runtime, and diagnostic testing confirmed the occurrence of CH1 interrupt loss. The issue is resolved when either the CH3 interrupt is disabled or CH3 is migrated to PIT0 (with only CH1 interrupt remaining on PIT1). Please assist in diagnosing the root cause of this interrupt loss issue. The MCAL driver version in use is SW32K3_RTD_4.4_2.0.0.
