PDB ADC pre trigger sequence error recovery

[Jarvis_vk]

Hi NXP community,

ADC0/ADC1 Interrupts Stop After Runtime Flash Erase/Program Operation on S32K144

As a continuation of my previous question, I need some clarification on how to properly recover from a PDB ADC pre-trigger sequence error on the S32K144.

I tried the following three methods, but only one of them worked correctly.

Method 1 (working):

• Stop PDB0 and PDB1 before performing the flash erase/program operation.
• After the flash operation is complete, restart both PDBs and re-enable the corresponding ISRs.

With this approach, no PDB sequence error occurs.

Method 2:

After the flash erase/program operation was completed, I stopped and restarted PDB0 and PDB1. However, a PDB pre-trigger sequence error occurred. I then attempted to recover by stopping and restarting the PDB modules again, but the sequence error persisted.

Method 3:

Method 3 (Not Working):

I did not stop or restart PDB0 and PDB1 during the flash erase/program operation. Instead, after the operation completed, one pending PDB ISR and ADC ISR were triggered.

Inside the PDB ISR, I attempted to clear the sequence error flag using:

PDB0->CH[0].S &= (uint32_t)(~PDB_S_ERR_MASK);

The corresponding ADC ISR was then executed, and reading the ADC result register cleared the COCO flag. I expected this to prevent further pre-trigger sequence errors, but the issue still persisted and this method did not work.

My question is: once a PDB pre-trigger sequence error has been triggered, is it possible to recover the PDB/ADC operation and resume normal triggering without resetting the system? Or does the PDB need to be stopped and restarted beforehand to avoid entering an unrecoverable state?

[PetrS]

Hi,

Clearing PDB_S_ERR alone is usually not sufficient to recover from a pre-trigger sequence error because the ADC/PDB sequence may already be out of synchronization. Based on your test results, preventing the condition by stopping the PDB before the flash operation and restarting it afterwards appears to be the most reliable approach.

If recovery is attempted after the error occurs, I would recommend ensuring that both the PDB and ADC state are fully re-synchronized. This may include disabling the PDB, clearing pending PDB status flags, ensuring all pending ADC conversion results have been read (COCO cleared), re-enabling the PDB, and reloading the configuration if required before triggering resumes.

According to the RM, the pre-trigger lock is released when the corresponding COCO flag is set, when the pre-trigger is disabled, or when the PDB is disabled, so a full PDB disable/enable sequence may also be worth investigating.

BR, Petr

[Jarvis_vk]

Hi PetrS,

I tried the following approach.

After the flash erase operation without PDB stop, micro got one pending ADC ISR callback. Inside that callback, after reading the ADC result register, I call the functions below to check and recover from a PDB sequence error:

```c
void PDB1_check_seq_err(void)
{
if ((PDB1->CH[0].S & PDB_S_ERR_MASK) != 0)
{
PDB1->CH[0].S &= (uint32_t)(~PDB_S_ERR_MASK);
PDB1->SC &= (uint32_t)(~PDB_SC_PDBEN_MASK);
PDB1->SC |= (uint32_t)PDB_SC_PDBEN_MASK;
PDB1->SC |= (uint32_t)PDB_SC_SWTRIG_MASK;

}
}

void PDB0_check_seq_err(void)
{
if ((PDB0->CH[0].S & PDB_S_ERR_MASK) != 0)
{
PDB0->CH[0].S &= (uint32_t)(~PDB_S_ERR_MASK);
PDB0->SC &= (uint32_t)(~PDB_SC_PDBEN_MASK);
PDB0->SC |= (uint32_t)PDB_SC_PDBEN_MASK;
PDB0->SC |= (uint32_t)PDB_SC_SWTRIG_MASK;
}
}
```

The recovery sequence I used is:

1. Clear the `ERR` flag.
2. Stop the PDB.
3. Re-enable and restart the PDB.

With this stop-and-start sequence, everything works correctly again: subsequent pre-triggers occur, and the ADC ISR callbacks are invoked normally.

However, I still do not fully understand why this is necessary. The Reference Manual states that clearing the `ERR` condition and reading the ADC result register (which clears `COCO`) should release the lock. In my case, that alone does not seem to be sufficient, and a PDB stop/start sequence is required for recovery.

Also, I observed that `PDBn->SC |= PDB_SC_SWTRIG_MASK` is not strictly required. Even without issuing a software trigger, the lock is released and the ADC ISR starts executing again after the PDB restart.

Could you please clarify why stopping and restarting the PDB is necessary in this scenario, even though the RM indicates that clearing `ERR` and `COCO` should release the lock?