Need help about S32K144_LPIT_DMA_LPSPI

[YF_LYW]

Hi:

I debug Example_S32K144_LPIT_DMA_LPSPI_DS22_v1 in S32K144 EVB-Q100. And i have some issues about SPI-dma function:

1.why the example stopped by DMA-ES-SGE error and TCD0-DADDR is wrong when 64 bytes has been tramsimit.

2.why the DMA ISR occurs when 32 bytes has been tramsimitted.

3.Whether DMA-SPI can be triggered by software insted of LPIT. Is there some demo project.

Thanks a lot for anyone reply.

YF_LYW_0-1695791788583.png

[danielmartynek]

Hi @YF_LYW,

If you don't need the periodic LPIT trigger for the DMA, you can refer to the lpspi_dma_s32k144 SDK example.

danielmartynek_0-1695829512719.png

The transfer is triggered by this function:  

danielmartynek_1-1695829596532.png

Regards,

Daniel

[YF_LYW]

Hi @danielmartynek 

Thanks for your quick reply. I study the example which you refer. And I find there are will be some data skipped in SPI-DMA. And I slow down the transmit speed as 1Mhz, almost half receive data is lost.  

Could you give me some hints for this problem? 

YF_LYW_0-1696659565582.png

YF_LYW_1-1696660100034.png

[danielmartynek]

Hi @YF_LYW,

Can you test the following:

• Lower the baudrate
• Set High-drive strength of the pins used for the SPI (both Master and Slave).danielmartynek_0-1696927709330.png
• Disable the SAMPLE feature

LPSPI_DRV_MasterInit(SEND, &SendState, &Send_MasterConfig0);
LPSPI0->CFGR1 &= ~(LPSPI_CFGR1_SAMPLE_MASK);

Do you monitor the bus with a logic analyzer?

Regards,

Daniel

[YF_LYW]

hi @danielmartynek 

I modify the configuration as you suggested and slow down the transfer speed to 100k, the data is all matched and there is no data skipped.

Can you tell me reason why this configuration can fix this issue.

Thanks a lot.

[danielmartynek · Accepted solution]

The electrical characteristics of the bus can distorted the signals.

It is recommended to use GPIO-HD pins that provide better slew rate especially at higher baudrates.

danielmartynek_0-1696931951723.png

If SAMPLE = 1, the Master samples the external delayed SCK that can be distorted, not the internal signal.

danielmartynek_1-1696932067499.png

Make sure the signals on the bus are within the specs.

DS, Table 46. LPSPI electrical specifications

Regards,

Daniel

[YF_LYW]

Hi @danielmartynek 

Thanks for you patience reply.