NXP RTOS Example Issue for S32K344 - build mode

[MVR]

Hello all,

I would like to understand why the example "RTOS_example_S32K344_SC1" is not possible to build using Debug_Flash. Does anyone know it?

Is it possible to build with Debug_Flash? If yes, how?

I'm using RTD 4.0.0 and S32DS 3.5 versions.

I added new features on the example and I'm facing this error:

Thanks,

MVR

[VaneB]

Hi @MVR 

Sorry for the late response, due to workload my response was delayed.

Firstly, I must clarify that the software has code drop quality, its functionality is not completely tested, so it is not recommended for production.

The examples of this software are delivered only with RAM Linker File, so when you want to load it to Flash it will not be possible because the file required for this is not tested.

I apologize for the inconvenience.

[MVR]

Hello @VaneB thank you for your answer.

Do you have any perspective when we will have the project building on Debug_FLASH?

Thanks.

[VaneB]

Hi @MVR 

I am afraid that at this moment we have no information regarding when a new version of the software will be released that tests all the files necessary for this.

[MVR]

Anyone, please?

[VaneB]

Hi @MVR 

Sorry for the inconvenience. 

I have not been able to face the same error as the ones shown in the images shared. Could you please provide me with your exact RTD package version? This is to be in the same context and to try to replicate your problem. 

[MVR]

Forget the error that I sent, I wanted to show the error only because I would like to use Debug_FLASH in the build configuration. So the main issue is: I would like to compile the NXP RTOS example code in Debug_FLASH mode and not Debug_RAM, can you provide the example compiling with Debug_FLASH, please?

I'm using this RTD:

S32K3x_NXP_RTOS_4_7_152_CODEDROP_0_4_1_DS_updatesite_D2312

and

S32K3_S32M27x Real-Time Drivers AUTOSAR R21-11 Version 4.0.0

This is the example that I would like to compile using Debug_FLASH:

Thanks,

MVR

[MVR]

Basically @not_a_duck and @VaneB , I would like a linker file to use with flash for NXP RTOS project, is it possible?

This is the current linker file for NXP RTOS example (RAM).

/**************************************************************************************

*

*   NXP(TM) and the NXP logo are trademarks of NXP

*   All other product or service names are the property of their respective owners.

*   Copyright 2020-2023 NXP

*   All Rights Reserved.

*

*   You can use this example for any purpose on any computer system with the

*   following restrictions:

*

*   1. This example is provided "as is", without warranty.

*

*   2. You don't remove this copyright notice from this example or any direct derivation

*      thereof.

*

*  Description:  GCC linker command file for NXP RTOS sample application

*

**************************************************************************************/

MEMORY 

{

    OsInternalRAM :   org = 0x20400000, len = 0x20000    /* 128K should be enough for sample */

}

SECTIONS

{

     /* Interrupt vectors table */

    .all :

    {

    *(.vector)

    *(.startup)         /* reset code */

    *(.systeminit)      /* SystemInit */

    *(.text.startup)

    /* Code and constant area (all code and constant sections shall be placed between .osbegincode and .osendcode sections). */

    . = ALIGN(0x20);

    *(.osbegincode)  /* for mem protection only */

    *(.ostext)

    *(.oshook)

    *(.osrodata)

    *(.syscall)

    *(.secinfo)

    *(.rodata)

    *(.ossrodata)

    *(.sapp_c32)

    *(.sapp_c16)

    *(.sapp_cU)

    *(.sapp_c8)

    *(.text)

    *(.appcode)

    *(.ROM.data)

    *(.osendcode)    /* for mem protection only */

    /* ------------------------------------ OS stack area ------------------------------------ */

    . = ALIGN(0x20);

    *(.osstack)

    /* -------------------------------------- Default data/bss --------------------------------- */

    *(.data)

    *(.osdata)                           /* it is empty */

    *(.ossdata)

    . = ALIGN(0x20);

    *(.sapp_v32_data)

    *(.sapp_v16_data)

    *(.sapp_vU_data)

    *(.sapp_v8_data)

    /* ------------------------------------ BSS sections ------------------------------------ */

    _bss_start = .;

    *(.osbss)

    *(.ossbss)

    . = ALIGN(0x20);

    *(.bss)

    *(.sbss)

    . = ALIGN(0x20);

    *(.sapp_v32_bss)

    *(.sapp_v16_bss)

    *(.sapp_vU_bss)

    *(.sapp_v8_bss)

    _bss_end = .;

    /* ------------------------------------ main stacks section ------------------------------------ */

    . = ALIGN(16);

    _Stack_end  = .;

    OS_MAIN_STACK_MIN = .;

    KEEP(*(.stack_main))

    _Stack_start = .; /* stack grows downward */

    OS_MAIN_STACK_MAX  = .;

. = ALIGN(0x80); /* Reserved */

    } >OsInternalRAM

}

[not_a_duck]

Should look something along the lines of this:

/**************************************************************************************
*
*   NXP(TM) and the NXP logo are trademarks of NXP
*   All other product or service names are the property of their respective owners.
*   Copyright 2020-2023 NXP
*   All Rights Reserved.
*
*   You can use this example for any purpose on any computer system with the
*   following restrictions:
*
*   1. This example is provided "as is", without warranty.
*
*   2. You don't remove this copyright notice from this example or any direct derivation
*      thereof.
*
*  Description:  GCC linker command file for NXP RTOS sample application
*
**************************************************************************************/
MEMORY 
{
    OsInternalRAM :   org = 0x20400000, len = 0x20000    /* 128K should be enough for sample */
    OsFLASH       : org = 0x00400000, len = 0x003D4000    /* 4096KB - 176KB (sBAF + HSE)*/
}
 
 
SECTIONS
{
 
     /* Interrupt vectors table */
    .all :
    {
 

 
    /* Code and constant area (all code and constant sections shall be placed between .osbegincode and .osendcode sections). */
    . = ALIGN(0x20);
    *(.osbegincode)  /* for mem protection only */
 
    *(.osrodata)
    *(.secinfo)
    *(.rodata)
    *(.ossrodata)
    *(.sapp_c32)
    *(.sapp_c16)
    *(.sapp_cU)
    *(.sapp_c8)
    *(.ROM.data)
 
 
    *(.osendcode)    /* for mem protection only */
 
    
    /* ------------------------------------ OS stack area ------------------------------------ */
    . = ALIGN(0x20);
    *(.osstack)
 
    /* -------------------------------------- Default data/bss --------------------------------- */
    *(.data)
    *(.osdata)                           /* it is empty */
    *(.ossdata)
 
    . = ALIGN(0x20);
    *(.sapp_v32_data)
    *(.sapp_v16_data)
    *(.sapp_vU_data)
    *(.sapp_v8_data)
 
    /* ------------------------------------ BSS sections ------------------------------------ */
    _bss_start = .;
    *(.osbss)
    *(.ossbss)
 
    . = ALIGN(0x20);
    *(.bss)
    *(.sbss)
 
    . = ALIGN(0x20);
    *(.sapp_v32_bss)
    *(.sapp_v16_bss)
    *(.sapp_vU_bss)
    *(.sapp_v8_bss)
 
    _bss_end = .;
 
 
    /* ------------------------------------ main stacks section ------------------------------------ */
    . = ALIGN(16);
    _Stack_end  = .;
    OS_MAIN_STACK_MIN = .;
 
    KEEP(*(.stack_main))
 
    _Stack_start = .; /* stack grows downward */
    OS_MAIN_STACK_MAX  = .;
 
. = ALIGN(0x80); /* Reserved */
    } >OsInternalRAM

    .flash_code :
    {
        // the begining of flash is for the boot header
        KEEP(*(.boot_header))
        . = ALIGN(2048);
        *(.vector)
        *(.startup)         /* reset code */
        *(.systeminit)      /* SystemInit */
        *(.text.startup)
        *(.ostext)
        *(.oshook)
        *(.syscall)
        *(.text)
        *(.appcode)
    } > OsFLASH
}

make sure that you have the .boot_header section as part of your image. this needs to be at 0x400000.
(can also be at 0x500000, 0x600000, 0x700000 or 0x10000000)

.section ".boot_header","ax"
  .long SBAF_BOOT_MARKER /* IVT marker */
  .long (CM7_0_ENABLE << CM7_0_ENABLE_SHIFT) | (CM7_1_ENABLE << CM7_1_ENABLE_SHIFT) | (CM7_2_ENABLE << CM7_2_ENABLE_SHIFT) /* Boot configuration word */
  .long 0 /* Reserved */
  .long CM7_0_VTOR_ADDR /* CM7_0 Start address */
  .long 0 /* Reserved */
  .long CM7_1_VTOR_ADDR /* CM7_1 Start address */
  .long 0 /* Reserved */
  .long CM7_2_VTOR_ADDR /* CM7_2 Start address */
  .long 0 /* Reserved */
  .long XRDC_CONFIG_ADDR /* XRDC configuration pointer */
  .long LF_CONFIG_ADDR /* Lifecycle configuration pointer */
  .long 0 /* Reserved */

[MVR]

Anyone?

[not_a_duck]

Can you share your linker file?
What is the size of the "OsInternalRam" region. It seems odd that you would be running out of RAM. the s32k344 has quite a lot. 

[VaneB]

Hi @MVR 

Did you face the same behavior without making changes to the example code? Could you share the modifications made? 

B.R.

VaneB

[MVR]

With the original example, we are able to build only using DEBUG_RAM.

if we change to DEBUG_FLASH, we get a lot of errors.

I need to use in my project, DEBUG_FLASH, once using DEBUG_RAM, I get error about overflow, as I sent on screenshot. But if we fix the error already in the example, I can do the same in my project. I only need to build the project with NXP RTOS using DEBUG_FLASH.

Did you get it @VaneB ? Do you still need the example code without change?

thanks,

MVR

[not_a_duck]

is it possible that you are building an image for RAM instead of FLASH. It seems that your app is too large to fit in RAM so it should not be built for that; only for flash.

[MVR]

Yeah, I know. But when we are using NXP RTOS, we can’t build with FLASH mode… if we change to Flash, I get a lot of errors

[not_a_duck]

@MVR It seems that your app is too large to fit in RAM. If this statement is true, then that leaves you with two options:

1. You reduce the code size of your app.
   1. You can do that manually by remove code you don't need.
   2. Or you can use the -Os compiler option which is the same as -O2 (without optimizations that increase code size)
2. You move your code to flash. (which i would advise you to do)

What sorts of errors are you seeing when you are building you app for flash?

[MVR]

The main question here is that I need to move to FLASH. But the example NXP RTOS is not possible to move to FLASH. This is the problem…

[not_a_duck]

You need to define plfash as a section in your memory region.

/*
* GCC Linker Command File:  This linker is demo and  is not part of the production code deliverables.
* 0x00000000    0x0000FFFF  65536   ITCM
* 0x20000000    0x2001FFFF  131072  DTCM
* 0x00400000    0x007FFFFF  4194304 Program Flash
* 0x10000000    0x1001FFFF  131072  Data Flash
* 0x20400000    0x20427FFF  163840  SRAM_0
* 0x20428000    0x20443FFF  114688  SRAM_1  /* Actually 112 kB instead of 160KB in RM
* Last 176 KB of CODE_FLASH reserved by HSE Firmware
* standby_data section should contain only uninitialized data
*/
HEAP_SIZE  = DEFINED(__heap_size__)  ? __heap_size__  : 0x00002000;
__STANDBY_RAM_LIMIT_END  = 0x20407FFF;  /* 32Kbyte for standby ram */

ENTRY(Reset_Handler)

MEMORY
{
    int_pflash              : ORIGIN = 0x00400000, LENGTH = 0x003D4000    /* 4096KB - 176KB (sBAF + HSE)*/
    int_dflash              : ORIGIN = 0x10000000, LENGTH = 0x00020000    /* 128KB */
    int_itcm                : ORIGIN = 0x00000000, LENGTH = 0x00010000    /* 64KB */
    int_dtcm                : ORIGIN = 0x20000000, LENGTH = 0x0001F000    /* 124KB */
    int_stack_dtcm          : ORIGIN = 0x2001F000, LENGTH = 0x00001000    /* 4KB */
    int_sram                : ORIGIN = 0x20400000, LENGTH = 0x0002FF00    /* 184KB, needs to include int_sram_fls_rsv */
    int_sram_fls_rsv        : ORIGIN = 0x2042FF00, LENGTH = 0x00000100
    int_sram_no_cacheable   : ORIGIN = 0x20430000, LENGTH = 0x0000FF00    /* 64KB, needs to include int_sram_results  */
    int_sram_results        : ORIGIN = 0x2043FF00, LENGTH = 0x00000100
    int_sram_shareable      : ORIGIN = 0x20440000, LENGTH = 0x00004000    /* 16KB */
    ram_rsvd2               : ORIGIN = 0x20444000, LENGTH = 0             /* End of SRAM */
}

and then instead putting your code into the sram region you had defined in your linker script you need to include it in the int_plfash region

[MVR]

The linker for RAM is different for NXP RTOS, I tried it that you recommended but it didn't work... I think we need to adapt more things.