Media clock generation using eDMA

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Media clock generation using eDMA

239 Views

Hello Everyone,

I’m working on generating a clock using the GMAC PPS module along with eDMA.

From the documentation, I understand that the mcgr_dma_req_o[3:0] signal gets asserted when the GMAC system time is greater than or equal to the configured target time.

   

sathishkumar_sunmugavel_0-1753271626406.png

 

sathishkumar_sunmugavel_1-1753271663068.png

 

My goal is to use this signal to trigger eDMA to automatically update the next target time by copying values into the following registers:

  • MAC_PPS0_TARGET_TIME_NANOSECONDS

  • MAC_PPS0_TARGET_TIME_SECONDS

I would like to clarify:

  • How do I connect mcgr_dma_req_o to the DMA controller? How eDMA will receive Peripheral Request?

  • Are these signals internally routed to the DMA MUX in the MCU, or do I need to configure any specific routing?

If anyone has any examples, reference configurations, or application notes for this kind of setup, please share.

The intended behavior is:
Whenever the GMAC system time reaches the current target time, the mcgr_dma_req_o signal triggers a DMA transfer that updates the target time for the next PPS event.

Thanks in Advance!!!

0 Kudos
Reply
0 Replies
%3CLINGO-SUB%20id%3D%22lingo-sub-2139381%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3EMedia%20clock%20generation%20using%20eDMA%3C%2FLINGO-SUB%3E%3CLINGO-BODY%20id%3D%22lingo-body-2139381%22%20slang%3D%22en-US%22%20mode%3D%22CREATE%22%3E%3CP%3E%3CSTRONG%3EHello%20Everyone%2C%3C%2FSTRONG%3E%3C%2FP%3E%3CP%3EI%E2%80%99m%20working%20on%20generating%20a%20clock%20using%20the%20%3CSTRONG%3EGMAC%20PPS%20module%3C%2FSTRONG%3E%20along%20with%20%3CSTRONG%3EeDMA%3C%2FSTRONG%3E.%3C%2FP%3E%3CP%3EFrom%20the%20documentation%2C%20I%20understand%20that%20the%20mcgr_dma_req_o%5B3%3A0%5D%20signal%20gets%20asserted%20when%20the%20%3CSTRONG%3EGMAC%20system%20time%3C%2FSTRONG%3E%20is%20%3CSTRONG%3Egreater%20than%20or%20equal%20to%20the%20configured%20target%20time%3C%2FSTRONG%3E.%3CBR%20%2F%3E%3CBR%20%2F%3E%26nbsp%3B%20%26nbsp%3B%3C%2FP%3E%3CP%3E%3CSPAN%20class%3D%22lia-inline-image-display-wrapper%20lia-image-align-inline%22%20image-alt%3D%22sathishkumar_sunmugavel_0-1753271626406.png%22%20style%3D%22width%3A%20400px%3B%22%3E%3Cspan%20class%3D%22lia-inline-image-display-wrapper%22%20image-alt%3D%22sathishkumar_sunmugavel_0-1753271626406.png%22%20style%3D%22width%3A%20400px%3B%22%3E%3Cimg%20src%3D%22https%3A%2F%2Fcommunity.nxp.com%2Ft5%2Fimage%2Fserverpage%2Fimage-id%2F349116i96F3AB10FF264538%2Fimage-size%2Fmedium%3Fv%3Dv2%26amp%3Bpx%3D400%22%20role%3D%22button%22%20title%3D%22sathishkumar_sunmugavel_0-1753271626406.png%22%20alt%3D%22sathishkumar_sunmugavel_0-1753271626406.png%22%20%2F%3E%3C%2Fspan%3E%3C%2FSPAN%3E%3C%2FP%3E%3CBR%20%2F%3E%3CP%3E%3CSPAN%20class%3D%22lia-inline-image-display-wrapper%20lia-image-align-inline%22%20image-alt%3D%22sathishkumar_sunmugavel_1-1753271663068.png%22%20style%3D%22width%3A%20400px%3B%22%3E%3Cspan%20class%3D%22lia-inline-image-display-wrapper%22%20image-alt%3D%22sathishkumar_sunmugavel_1-1753271663068.png%22%20style%3D%22width%3A%20400px%3B%22%3E%3Cimg%20src%3D%22https%3A%2F%2Fcommunity.nxp.com%2Ft5%2Fimage%2Fserverpage%2Fimage-id%2F349117iB4882C920349CB0B%2Fimage-size%2Fmedium%3Fv%3Dv2%26amp%3Bpx%3D400%22%20role%3D%22button%22%20title%3D%22sathishkumar_sunmugavel_1-1753271663068.png%22%20alt%3D%22sathishkumar_sunmugavel_1-1753271663068.png%22%20%2F%3E%3C%2Fspan%3E%3C%2FSPAN%3E%3C%2FP%3E%3CBR%20%2F%3E%3CP%3EMy%20goal%20is%20to%20use%20this%20signal%20to%20%3CSTRONG%3Etrigger%20eDMA%3C%2FSTRONG%3E%20to%20automatically%20update%20the%20next%20target%20time%20by%20copying%20values%20into%20the%20following%20registers%3A%3C%2FP%3E%3CUL%3E%3CLI%3E%3CP%3EMAC_PPS0_TARGET_TIME_NANOSECONDS%3C%2FP%3E%3C%2FLI%3E%3CLI%3E%3CP%3EMAC_PPS0_TARGET_TIME_SECONDS%3C%2FP%3E%3C%2FLI%3E%3C%2FUL%3E%3CP%3EI%20would%20like%20to%20clarify%3A%3C%2FP%3E%3CUL%3E%3CLI%3E%3CP%3EHow%20do%20I%20connect%20mcgr_dma_req_o%20to%20the%20DMA%20controller%3F%20How%20eDMA%20will%20receive%20Peripheral%20Request%3F%3C%2FP%3E%3C%2FLI%3E%3CLI%3E%3CP%3EAre%20these%20signals%20internally%20routed%20to%20the%20DMA%20MUX%20in%20the%20MCU%2C%20or%20do%20I%20need%20to%20configure%20any%20specific%20routing%3F%3C%2FP%3E%3C%2FLI%3E%3C%2FUL%3E%3CP%3EIf%20anyone%20has%20any%20%3CSTRONG%3Eexamples%3C%2FSTRONG%3E%2C%20%3CSTRONG%3Ereference%20configurations%3C%2FSTRONG%3E%2C%20or%20%3CSTRONG%3Eapplication%20notes%3C%2FSTRONG%3E%20for%20this%20kind%20of%20setup%2C%20please%20share.%3C%2FP%3E%3CP%3EThe%20intended%20behavior%20is%3A%3CBR%20%2F%3EWhenever%20the%20%3CSTRONG%3EGMAC%20system%20time%20reaches%20the%20current%20target%20time%3C%2FSTRONG%3E%2C%20the%20mcgr_dma_req_o%20signal%20triggers%20a%20%3CSTRONG%3EDMA%20transfer%3C%2FSTRONG%3E%20that%20updates%20the%20target%20time%20for%20the%20next%20PPS%20event.%3CBR%20%2F%3E%3CBR%20%2F%3EThanks%20in%20Advance!!!%3C%2FP%3E%3C%2FLINGO-BODY%3E