MR-CANHUBK344 SPI Setup

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MR-CANHUBK344 SPI Setup

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sethappleman
Contributor I

I have a MR-CANHUBK344. I am using the generic 7-wire JST-GH cable to connect SPI port P1A to P1B so that I can demo the exchange of SPI data locally within the same SW package. P1A and P1B map to modules LPSPI1 and LPSPI2, respectively.

I am configuring the following pins:

GPIO21: LPSPI1_PSC0 (output)

GPIO28: LPSPI1_SCK (output)

GPIO29: LPSPI1_SIN (input)

GPIO30: LPSPI_SOUT (output)

GPIO57: LPSPI2_PSC0 (input)

GPIO59: LPSPI_SOUT (input)

GPIO60: LPSPI_SIN (output)

GPIO61: LPSPI_SCK (input)

 

To account for the wiring of the cable, in which LPSPI1_SOUT connects to LPSPI2_SOUT, and LPSPI1_SIN connects to LPSPI2_SIN, I set LPSPI2.CFGR1.PINCFG = 3 (SOUT used for input, SIN used for output).

 

Aside from this I am trying to follow the S32 Design studio example as closely as I can (Lpspi_Ip_HalfDuplexTransfer_S32K396). Are there any additional considerations in either SW or HW I need to take into account with the setup I am trying to demonstrate?

 

Currently I am unable to see any data sent from LPSPI1 show up in the RX FIFO of LPSPI2.

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VaneB
NXP TechSupport
NXP TechSupport

Hi @sethappleman 

As you are working with a four-wire (full duplex) mode by default, SIN is input and SOUT is output. Changing the SIN/SOUT configuration should be done via LPSPI->CFGR1[PINCFG]; in case of ConfigTools, this configuration should be done in the Lpspi driver under SpiGeneral > SpiPhyUnit > SpiPinConfiguration.

VaneB_0-1731433929235.png

Also, for Lpspi driver configuration, you can refer to the example provided in the following thread, it may be a good reference for you.

Example S32K344 SPI Transmit & Receive Using DMA DS3.5 RTD500

 

BR, VaneB

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sethappleman
Contributor I

Thank you I will refer to your link. I failed not mention that while I am using the S32 Design studio project code I referenced as a guide, I am not using the S32 DS tool itself to develop for the MR-CANHUBK344 dev board. The nature of the restrictions on the project on which I am working prevents me from doing so.

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VaneB
NXP TechSupport
NXP TechSupport

Hi @sethappleman 

If the problem persists, please let me know.

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