I see the problem - there is an inconsistency in the clock configuration.
danielmartynek_0-1750236224341.png
The modules is clocked by 8MHz from SIRCDIV2_CLK.
But the UART module calculates the baudrate from ReferencePoint_0 which is 48MHz.
danielmartynek_1-1750236286676.png
danielmartynek_2-1750236435331.png
Regards,
Daniel