LPSPI for Slave Mode Communication

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LPSPI for Slave Mode Communication

Contributor I

Hi Support Team,

In one of the project S32K144 is slave device. There will be a big chunk of data transfer between master and S32K slave.(64 Bytes of data in one chip select assertion ) and this will be a period frame for every 10ms.

I want you suggestion which method is optimal for this communication.? Interrupt of DMA ?

First i want to try interrupt method. (DMA is new for me)

Configuration for this as per my understanding.

  • Set module in slave mode
  • Set chip select polarity
  • TX and RX FIFO water mark
  • Chip select, clock polarity, clock phase, prescaler, Msb first, frame size(32bit)
  • Enable interrupt for receive data RDIE. (No TX interrupt)
  • Enable LPSPI module.

As per datasheet,

Point 1. Slave Mode: Before the LPSPI_PCS input asserts, the transmit FIFO must be filled with
transmit data, or the transmit error flag will set? I did not understand this point. I am implementing my own code, but I referred SDK code, i do not see above point(Point 1) taken care in SDK.

I need your input regarding this point.

Point 2. Slave Mode: AUTOPCS bit config register 1(CFGR1), Is this bit need to be set for Slave mode ? 

I need your inputs for above two points and please correct me if am missing anything in configuration.

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NXP TechSupport
NXP TechSupport

This is up to you whether you use interrupts or DMA.
You can refer to SDK examples: lpspi_transfer_s32k144 & lpspi_dma_s32k144

The lpspi_tranfer uses interrupts.
If you halt the example after the slave transfer function, you can see all the registers configuration of the slave (LPSPI1).


Also, in the example, the slave data are prepared before the MasterTrasferBlocking function is called.


No, the AUTOPCS bit doesn’t need to be set.



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Contributor I

Hi Daniel,

Thanks for you response.

For me LPSPI as slave is not working. Meaning RX interrupt is not working.

I tried to Poll RDF flag but no use.

I checked Spi lines from master to LPSPI slave on CRO. I am able to observe CS, CLK and Data.  

Please find the attached code and debugger snap shot for configuration.

Please help me understanding what i am missing in configuration.


Note. Verified Port pins for alternate function configuration.

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