LPSPI CLK

[Psabouri]

Hi,

I have a S32K344 evaluation board. I am configuring the LPSPI_0 to transfer 16-bit data at 8MHz. The CLK is outputted on PTC8 (standard plus pad).  As you can see in the figure below, the CLK periodicity is incorrect and it is changing!!! Why CLK is behaving like this?

LPSPI_0 functional clock is 80MHz

CCR1[SCKHLD] = CCR1[SCKSET] = 4

When the bus rate is decreased to 5MHz, the CLK behaves correctly.

[VaneB · Accepted solution]

Hi @Psabouri 

The problem may be in the configuration of your sample rate, you should increase the sample rate in order to have a better resolution of the clock signal. 

B.R.

VaneB

[Psabouri]

That make sense, thank you for your response.