Hi@Punit_01
This can be explained.
For details, you can refer to S32K-RM Chapter: 52.3.2.4 Timing Parameters
The SCL clock is not only determined by the module clock, but also affected by other parameters, including SCL_LATENCY,
The latency parameters are defined in the following table, these parameters assume the
risetime is less than one LPI2C functional clock cycle. The risetime depends on a number
of factors, including the I/O propagation delay, the I2C bus loading and the external pullup
resistor sizing. A larger risetime will increase the number of cycles that the signal
takes to propagate through the synchronizer (and glitch filter), which increases the
latency.
In summary, the difference in the electrical characteristics of the external circuit will also affect the SCK.
