How to use S32K344 BIST?

[li3]

Hi NXP,

Please help me answer the questions related to S32K344 BIST.

1. How to start BIST?

2. How to configure LBIST and MBIST?

3. Which register is the result to check after the execution?

4. How to configure the BIST for the next reset?

5. Where should the code be written?

Best regards,

Li 3.

[Julián_AragónM]

Hi @li3,

After installing the SAF evaluation, you can find the BIST user manual and an .xlsx file for Bist configuration under "C:\NXP\S32K3_SAF_1.0.4_EVAL_D2312\eclipse\plugins\Bist_TS_T40D34M10I4R0\doc"

Best regards,
Julián

[li3]

Hi NXP,

1.I do not understand the introduction of BIST_SAFETYBOOT_CFG and BIST_DIAGNOSTIC_CFG in the chip manual, please tell me the difference between them?

2.Should I use BIST_SAFETYBOOT_CFG or BIST_DIAGNOSTIC_CFG when developing with s32k344 MCU?

Best regards,

Li 3.

[Julián_AragónM]

Hi @li3,

The difference between BIST_SAFETYBOOT_CFG and BIST_DIAGNOSTIC_CFG is when they would be triggered:

While BIST_SAFETYBOOT_CFG is supposed to be triggered right after the BootROM-HSE firmware execution in the startup, BIST_DIAGNOSTIC_CFG shall be triggered during runtime when no other (or just limited jobs) are in progress.

• The validation and verification team creates BIST_SAFETYBOOT_CFG as a compromise which takes less than 10ms and still has sufficient coverage. This configuration is recommended for the startup use case.  
• BIST_DIAGNOSTIC_CFG includes all the BIST available on the platform. Execution time is longer than 10ms, which is a timeslot for the startup BISTs. It means this configuration can be run in garage or don’t need to be run at all.

The execution flow between BIST_SAFETYBOOT_CFG and BIST_DIAGNOSTIC_CFG are pretty much identical, which you can find in 54.1.13 Self-Test programming sequence from the S32K3XX's Reference Manual.

You can also refer to these community posts:

• Not enough information about Supported BIST configurations for S32K396
• Solved: STCU2 internal errors and SPD-BIST BIST_DIAGNOSTIC_CFG - NXP Community

Best regards,
Julián

[li3]

Hi NXP,
Is the BIST_RUN(BIST_SAFETYBOOT_CFG) function called in the Main function? Or is it somewhere else?

Best regards,
Li 3.

[Julián_AragónM]

Hi @li3,

Safety Boot is supposed to be triggered from the custom bootloader/startup code that follows BootROM - HSE firmware execution, but you can basically call it whenever you like. After BIST you will have reset, and you will need initialize at least RAM.

You can also refer to the S32_SAF_Demo under the SAF package.

Best regards,
Julián

[li3]

Hi NXP，

1. The chip manual says that communication should be disabled when calling BIST_RUN(), so disable communication peripherals before calling BIST_RUN()?

2. After calling BIST_RUN(), the function RESET will be automatically. Is this the hardware automatically reset? Or do you need software to operate reset? If the hardware reset itself, please explain how the hardware triggers the reset?

3. See in the post BIST_SAFETYBOOT_CFG self-test MBIST1~11, BIST_DIAGNOSTIC_CFG self-test MBIST0~11 S32K344 What does MBIST0 do?

Best regards,

Li 3.

[Julián_AragónM]

Hi @li3,

1. Yes. This is needed in order to avoid an undesired/uncontrollable state.

2. Self-test execution ends by the functional reset. Please refer to the diagram below:

3. You can refer to chapter 54.1.3 STCU2 LBIST/MBIST mapping from the S32K3XX's reference manual.

Best regards,
Julián

[fede_ls]

2. Self-test execution ends by the functional reset. Please refer to the diagram below:

Hi @Julián_AragónM,

Can you confirm that every type of bist (MBIST or LBIST), regardless of being performed as BIST_SAFETYBOOT_CFG or BIST_DIAGNOSTIC_CFG leads to a functional reset? 

Is it due to the nature of the testing instances being invasive? Would it be possible to perform LBIST and MBIST without functional resets if I don't plan to use SAF?

For context, I want to perform both LBIST and MBIST(with MBIST only using a subset of IDs to test PRAM0+PRAM1 blocks and caches, ITCM and DTCM of both cores in a standard K344 lockstep configuration).

[li3]

Hi NXP,

1. What do PRAM0 block 1 and PRAM0 block 2 memory do in the figure below?

2. Why does the BIST_RUN(BIST_SAFETYBOOT_CFG) interface not self-check PRAM0 block 1 and PRAM0 block 2?

3. After calling BIST_RUN(), the interface will execute reset. Is this reset done by hardware or software?

Best regards,

Li 3

[Julián_AragónM]

Hi @li3,

1. There are 2 blocks of SRAM with an independent controller.

• PRAM0 controls the first 160 KB of RAM where 32 KB supports content retention in Standby mode and 128 KB is available only in Run mode
• PRAM1 Controls the second 160 KB and is available only in Run mode.

2. I'm not sure I understand this question. 

MBIST to detect permanent failures in SRAM either during start-up or from application SW or as part of fault recovery flow to localize faults.

LBIST to detect permanent failures in digital logic either during start-up or from application SW or as part of fault recovery flow to localize faults.

The Bist Index (Number of memories checked using memory built-in self-test controller) refers to PRAM0/1 (block 1 & 2) respectively.

3. As mentioned in the previous reply, the reset is done via SW through the Self-Test Control Unit.

Best regards,
Julián

[li3]

Please help me check the above questions, thank you.