How to configure the S32K344 dual-core operating mode

[FrankLiu2019]

Hi All,

I want to configure the S32K344 dual-core operating mode.I have already seen S32K344-LOCKTETP-EN .But the data I read is different from what's in the link.The first available space (all 0xFF) for a new record is at 0x1B000780,different from what's in the link.I write {0x00,0x01,0x00,0x00,0x04,0x00,0x10,0x00}at 0x1B000780,then the chip is locked.Can you tell me what's wrong?

This is my code

#include "Mcal.h"

#include "Clock_Ip.h"

#include "C40_Ip.h"

#include "IntCtrl_Ip.h"

#include "Siul2_Port_Ip.h"

#include "Lpuart_Uart_Ip.h"

#include "stdio.h"

#include "string.h"

#include "check_example.h"

#define FLS_MASTER_ID                0U

#define FLS_DCF_ADDR              0x1B000780U

#define FLS_SECTOR_DCF C40_UTEST_ARRAY_0_S000

#define FLS_BUF_SIZE                 160

#define FLS_DCF_START_ADDR           0x1B000700U

#define FLS_DCMROF_ADDR              0x402AC348U

#define UART3 3

#define UART_FLEXIO_TX_CHANNEL 0

#define UART_FLEXIO_RX_CHANNEL 1

#define MSG_LEN 50U

/*==================================================================================================

*                                      GLOBAL CONSTANTS

==================================================================================================*/

uint8 TxBuffer[8]={0x00,0x01,0x00,0x00,0x04,0x00,0x10,0x00};

uint8 RxBuffer[FLS_BUF_SIZE];

/*==================================================================================================

*                                   LOCAL FUNCTION PROTOTYPES

==================================================================================================*/

void Fls_InitBuffers(void);

void Fls_ExampleAssert(boolean Condition);

/**

 * @brief Implement a simple assert macro

 *

 * @Param  Condition

 * @return void

 */

void Fls_ExampleAssert(boolean Condition)

{

    while (!Condition)

    {

        /* Loop forever */

    }

}

/**

* @brief        Main function of the example

* @details      Initializes IP C40 driver and erase, write, read internal flash memory

*/

int main(void)

{

    uint32 Index;

    uint32 delay;

    (void)Index;

    C40_Ip_StatusType C40Status;

    Clock_Ip_StatusType ClockStatus;

    /* Initialize clock */

    ClockStatus = Clock_Ip_Init(&Clock_Ip_aClockConfig[0]);

    Fls_ExampleAssert(ClockStatus == CLOCK_IP_SUCCESS);

    /* Initialize C40 driver */

    C40Status = C40_Ip_Init(&C40ConfigSet_VS_0_InitCfg);

    Fls_ExampleAssert(STATUS_C40_IP_SUCCESS == C40Status);

    /* Initialize all pins */

    Siul2_Port_Ip_Init(NUM_OF_CONFIGURED_PINS0,g_pin_mux_InitConfigArr0);

    /* Initialize IRQs */

    IntCtrl_Ip_Init(&IntCtrlConfig_0);

    IntCtrl_Ip_ConfigIrqRouting(&intRouteConfig);

    /* Initializes an UART driver*/

    Lpuart_Uart_Ip_Init(UART3, &Lpuart_Uart_Ip_xHwConfigPB_3_VS_0);

    /* Unlock sector if needed */

    if(STATUS_C40_IP_SECTOR_PROTECTED == C40_Ip_GetLock(FLS_SECTOR_DCF))

    {

        C40_Ip_ClearLock(FLS_SECTOR_DCF, FLS_MASTER_ID);

        Lpuart_Uart_Ip_SyncSend(UART3,"unlock\r\n",8,50000);

    }

    /* Write data */

    C40_Ip_MainInterfaceWrite(FLS_DCF_ADDR, 8, TxBuffer, FLS_MASTER_ID);

    do

    {

        C40Status = C40_Ip_MainInterfaceWriteStatus();

        Lpuart_Uart_Ip_SyncSend(UART3,"Write",5,50000);

    }

    while (STATUS_C40_IP_BUSY == C40Status);

    Fls_ExampleAssert(STATUS_C40_IP_SUCCESS == C40Status);

    /* Read data */

    C40Status = C40_Ip_Read(FLS_DCF_ADDR, FLS_BUF_SIZE, RxBuffer);

    Lpuart_Uart_Ip_SyncSend(UART3,"Read\r\n",6,50000);

    /* Check job result */

    Fls_ExampleAssert(STATUS_C40_IP_SUCCESS == C40Status);

    Lpuart_Uart_Ip_SyncSend(UART3,(const uint8 *)RxBuffer,FLS_BUF_SIZE,50000);

    while(TRUE);

    /* If we get here it means the test has passed */

    Exit_Example(TRUE);

    return (0U);

}

[ALXY_WANG1]

I am also working on S32K344 dual-core decoupling mode, can you provide a sample project file of your successful decoupling?

[FrankLiu2019]

The data I read from 0x1B000768 is   D7 2A D5 82 50 00 04 00 D7 2A D5 82 70 00 04 00 D7 2A D5 82 B0 01 04 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ...So I write a new  record at 0x1B000780.

[davidtosenovjan]

An address to be written is correct, I have checked device we have here and it is the same (it is needed to use first erased area aligned to 64-bit).

A data to be written in order to disable locktesp are as folows:

#define PROGRAM_DATA1 (0x00100004) /* UTEST_MISC DCF Control Word */
#define PROGRAM_DATA0 (0x00000100) /* UTEST_MISC Data Word */

/* UTEST Miscellaneous Register */
uint32_t utest_misc_dcf[ ] = {
(uint32_t)PROGRAM_DATA0, /* DCF Data word 8h [0:31] */
(uint32_t)PROGRAM_DATA1 /* DCF Control word Ch [32:63] */
};

[FrankLiu2019 · Accepted solution]

Hi david

I've solved the problem.The chip is not actually locked, but after writing the DCF, the chip becomes s32k324, and the chip type needs to be changed to s32k324 to connect to it.

Thanks,

Frank

[FrankLiu2019]

Hi david

What I wrote is the same as yours,But it didn't work.Whether there are other operations to disable the lockstep,such as place the code in RAM,disable the MPU before programming,lock the UTEST Flash area after programming. Warm Reset after programming?

Thanks,

Frank