How to change core clock frequency of S32K144

[arvindupadhyay]

Hi friends,

How to change  core clock frequency of S32K144 in the range of 50 to 100MHz, I am trying to change but other modules clocks are affecting .I need 96MHz  core clock frequency of S32K144 for RTOS . If anyone knows please let me know.

Regards,

Arvind.

[Andre_b]

Hi

Anyone knows how to set the clock SPLL for using ADC by 50MHz?

Thank you so much

[PetrS]

Hi Arvind,

you can try this code to put MCU into HSRUN mode with PLL set to 96MHz

void clk_init(void)
{
    /* System clock initialization */

   /* SOSC Configuration */

    /* 8 MHz crystal */
    SCG->SOSCDIV = 0x00010101u; /* SCG_SOSCDIV: SOSCDIV3=1, SOSCDIV2=1, SOSCDIV1=1 */
    SCG->SOSCCFG = 0x00000034u; /* SCG_SOSCCFG: RANGE=3, EREFS=1 */
    while(SCG->SOSCCSR & 0x00800000u);
    SCG->SOSCCSR= 0x5u;         /* SCG_SOSCCSR: SOSCLPEN=1, SOSCEN=1 */
    while(!(SCG->SOSCCSR & 0x01000000u));

    /* SPLL Configuration 96 MHz */
    SCG->SPLLDIV = 0x00010101u; /* SCG_SPLLDIV: SPLLDIV3=1, SPLLDIV2=1, SPLLDIV1=1 */
    /* PREDIV = 0     8 MHz / 1 = 8 MHz */
    /* MULT   = 8     8 MHz / 1 * 24 = 192 MHz VCO */
    /* SOURCE = 0     system OSC (8 MHz) */
    SCG->SPLLCFG = 0x00080000;
    while(SCG->SPLLCSR & 0x00800000u);
    SCG->SPLLCSR=0x01;          /* SCG_SPLLCSR: SPLLEN=1 */
    while(!(SCG->SPLLCSR & 0x01000000u));

    /* configure  HSRUN mode */
    /* DIVCORE = 0;  CORE_CLK = 96 MHz */
    /* DIVPLAT = 0;   SYS_CLK = 96 MHz */
    /* DIVBUS  = 1;  BUS_CLK = 48 MHz */
    /* DIVSLOW = 3;  FLASH_CLK = 24 MHz */
    /* SCS = 6;      pll clock source */
    SCG->HCCR = 0x06000013;

    SMC->PMPROT = 0x80;    /* Allow high speed run */
    SMC->PMCTRL = 0x60;    /* Switch to high speed run */
    while(!(SMC->PMSTAT & 0x00000080u));
}

BR, Petr

[muhammadimranaf]

Hi Petr,

From above code I couldn't understand how you have calculated clock of 96MHz.

    /* SPLL Configuration 96 MHz */
    SCG->SPLLDIV = 0x00010101u; /* SCG_SPLLDIV: SPLLDIV3=1, SPLLDIV2=1, SPLLDIV1=1 */
    /* PREDIV = 0     8 MHz / 1 = 8 MHz */
    /* MULT   = 8     8 MHz / 1 * 24 = 192 MHz VCO */
    /* SOURCE = 0     system OSC (8 MHz) */
    SCG->SPLLCFG = 0x00080000;
    while(SCG->SPLLCSR & 0x00800000u);
    SCG->SPLLCSR=0x01;          /* SCG_SPLLCSR: SPLLEN=1 */
    while(!(SCG->SPLLCSR & 0x01000000u));

Actually I am trying to set system clock to 64Mhz and I couldn't get this code snippet. can you please explain abit.

Regards,

[cheukeichoy]

Hi Afzal,

   The clock path you need is below.

according to the descrition of the System PLL Configuration Register,you shoud be setting the MULT to 0, and setting PERDIV to 0.

so, you can try this code snippet. I hope I can help you.

    /* SPLL Configuration 64 MHz */
    SCG->SPLLDIV = 0x00010101u; /* SCG_SPLLDIV: SPLLDIV3=1, SPLLDIV2=1, SPLLDIV1=1 */
    /* PREDIV = 0     8 MHz / 1 = 8 MHz */
    /* MULT   = 0     8 MHz / 1 * (0+16) = 128 MHz VCO */
    /* SOURCE = 0     system OSC (8 MHz) */
    SCG->SPLLCFG = 0x00000000;
    while(SCG->SPLLCSR & 0x00800000u);
    SCG->SPLLCSR=0x01;          /* SCG_SPLLCSR: SPLLEN=1 */
    while(!(SCG->SPLLCSR & 0x01000000u));

   Regards,

   Cheukei