Flexcan, before send data, status the RAMn4 and RAMn5

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

Flexcan, before send data, status the RAMn4 and RAMn5

Jump to solution
372 Views
buccno
Contributor III

Hi, 
I wonder why this change happens. 

 

buccno_0-1671696271620.png

 

0 Kudos
1 Solution
347 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@buccno

Q1.you can take a look at the S32-RM Chapter 55.4.3 Message buffer structure-

>CODE->Message Buffer Code,

Both receiving and sending will query and update the CODE area.

Q2.You mean to parse a frame of data, which can be achieved by a shift operation, for example:

bit1~3 = (recvBuff.data[0] >> 1) & 0x07;;

View solution in original post

2 Replies
365 Views
buccno
Contributor III

I'm confused about one more thing, For example, I have a 64-bit length message with a single ID. how can I get bit 4.(starter bit),(length 4 bit), and bit (starter bit)50.(length 4 bit)?

0 Kudos
348 Views
Senlent
NXP TechSupport
NXP TechSupport

Hi@buccno

Q1.you can take a look at the S32-RM Chapter 55.4.3 Message buffer structure-

>CODE->Message Buffer Code,

Both receiving and sending will query and update the CODE area.

Q2.You mean to parse a frame of data, which can be achieved by a shift operation, for example:

bit1~3 = (recvBuff.data[0] >> 1) & 0x07;;