Deadtime Correction

[GaneshBhagwat]

Hi NXP Community,

I am looking for some clarification regarding the PWM-X deadtime correction feature.

From the documentation, I understand that PWM-X can modify the PWM pulses based on the current/load condition. However, I am not clear about how the PWM pattern is generated and how the required feedback signal is connected and routed.

In my application, the switches and current-sensing circuitry are external to the MCU:

• Is the sensed current signal expected to be connected directly to an MCU pin?

• Or should it first go through LPCMP and then be internally routed to PWM-X through TRGMUX or another internal connection?

• What is the expected signal path and configuration for this feature?

I have attached an image from the NXP reference design/documentation showing the slightly decaying output waveform obtained across the load.

What I am particularly trying to understand is the PWM pulse pattern used to generate this waveform.

The waveform shown in the reference design is the resulting waveform at the load/power stage. However, the PWM signal generated by the MCU will pass through the gate driver and switching stage, so the PWM signal itself will not have the same shape as the waveform shown.

PWM-X generated pulses → gate driver/power stage → resulting waveform across the load

Specifically, I would like to understand how PWM-X determines the pulse width/duty cycle and timing required to obtain the shown output waveform, including how the deadtime correction is applied.

Is there any reference design, application note, example code, or reference software where this PWM-X feature is implemented? An example showing the PWM configuration, pulse pattern, pin configuration, internal signal routing, and required external circuitry would be very helpful.

FlexPWM Synchronization

I also have a question regarding FlexPWM synchronization.

Can the synchronization signal be generated internally by another peripheral, or does it have to originate from an external MCU pin?

For example, can a signal generated by eMIOS be internally routed to the FlexPWM synchronization input?

Any example or clarification regarding the internal routing/configuration would be very helpful.

Thanks in advance.

Best regards,
Ganesh

[PetrS]

Hi,

The waveform shown in the reference manual is the voltage across the load during the deadtime interval. It is not a waveform generated directly by PWM_X. The shape results from the load current continuing to flow through the power-stage devices while both complementary switches are off.

For S32K396, the PWM period and duty cycle are still defined by the eFlexPWM counter and VAL registers, while DTCNT0/DTCNT1 control the inserted deadtime.

PWM_X is used as a feedback input for deadtime distortion measurement. The sampled PWM_X state is available through the deadtime status mechanism described in Sections 56.3.11.4-56.3.11.7, and the eCapture functionality described in Section 56.3.14 can be used to measure timing information related to these events.

The deadtime correction itself is not performed automatically by the eFlexPWM hardware. Instead, the application software is expected to evaluate the PWM_X feedback information and adjust the relevant PWM timing values (VAL registers) as needed.

The expected signal path is therefore:

Power-stage state or current-direction detection
↓
External signal conditioning / comparator
↓
PWM_X input
↓
Deadtime status bits and/or eCapture measurements
↓
Software correction algorithm
↓
Updated PWM timing values

PWM_X expects a digital signal. From the S32K396 routing options, LPCMP outputs cannot be internally connected to PWM_X through TRGMUX, therefore the required feedback signal must ultimately be provided on a pin configured as the corresponding PWM_X input.

Regarding synchronization, FlexPWM synchronization is not limited to an external signal source. On S32K396, an eMIOS-generated signal can be routed and used as a FlexPWM synchronization source, allowing synchronization to be implemented entirely internally without an external connection.

BR, Petr