DMA For ADC

[Ayaz]

I am using DMA to transfer data from FIFO1 and FIFO2 into a buffer. I am utilizing fixed DMA configurations for this data transfer. when completion of the transfer, the following functions will be called:

• Bctu_Ip_Bctu0Fifo1DmaComplete
• Bctu_Ip_Bctu0Fifo2DmaComplete

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The system functions correctly when I use an interrupt from RTD (IntCtrl_Ip_Init).

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However, for my project, I am using a different file to configure the interrupt handler, set priority, and enable the handler.

For DMA0_CH1 &DMA0_CH16,i am using IRQ : 

DMATCD1_IRQn / Dma0_Ch1_IRQHandler / Priority
DMATCD16_IRQn / Dma0_Ch16_IRQHandler / Priority

It works for BCTU_IRQn and PIT0_IRQn. It also works with DMA when it is triggered by PIT using the following configurations:
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However, it does not show any indication if the transfer has begun or not, and it is not raising an interrupt when the transfer is completed for DMA while reading data from FIFO using the fixed RTD configuration setup for DMA transfer (Bctu_FifoSetupDma).

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 What additional configurations are needed to get the system working?

[PetrS]

Hi,

not sure of the code you execute, probably just IntCtrl_Ip_InstallHandler and IntCtrl_Ip_EnableIrq. But the same is done in IntCtrl_Ip_Init as well.
Try to check/compare in debugger NVIC content and assigned handler in vector table for both ways.

BR, Petr

[Ayaz]

Hi@PetrS
I have tested the system and identified Destination Bus Errors on channels 1 and 16.”

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Do you have any idea about the cause of this ?

[PetrS]

Hi,

error may happen in case destination address points to memory range that is inaccessible - it means either access to reserved memory space or to disabled or un-clocked peripheral or protected by any kind of protection leading in bus error (MPU, XRDC).

BR, Petr

[Ayaz]

Hi@PetrS

Thanks for the information. Here is the list of clocks enabled in my project:

• TRGMUX
• BCTU 0
• eMIOS 0
• eMIOS 1
• eMIOS 2
• ADC 0
• ADC 1
• ADC 2
• PIT 0
• PUPD
• MC_ME_CTL_KEY_KEY(0x5AF0)
• MC_ME_CTL_KEY_KEY(0xA50F)
• eDMA - Control & Status
• eDMA - Transfer Control Descriptor 0 to 31
• DMA Channel Multiplexer 0
• DMA Channel Multiplexer 1
• MSCM
• STM0
• SIUL2
• CMU 0-6
• PLL
• FlexCAN 0 to 3
• LPI2C 0 to 1
• LPSPI 0 to 3
• CRC
• PCUD

1 )Does XRDC need clock enabling? If yes, can you provide the information on how to enable it?

2) Does Crossbar need clock enabling? If yes, can you provide the information on how to enable it?
3)Do i need to Adde Cache_Ip driver into the project ?

4)Are there any other clocks that need to be enabled?

[PetrS · Accepted solution]

Hi,

I do not expect issue with clock gating. You can check DMA TCD dest address if is has desired value.

1-2) No, it is always enabled
3) if Dcache is enabled and buffer not placed in non cacheable area, then you should use it flush/invalidate cache if needed
4) depend on application, if peripheral is used/accessed must not be clock gated. 

BR, Petr