I am facing few issues with the assembly code for the SAF library Scheck_Dma_RamBlockingTransfer and sCheck_CortexM7_ErrRead functions. We have a section In memory map for the int_sram_no_cacheable section where we keep all the three particular sections.
So the issue right now is I am having a working project with GHS based compiler with similar memory map and it is working good. when we add the BSW stack from third party on the base of working software then we are facing some issues, But the memory map file and everything are same and all the sections are looking good. I am not seeing any memory overlap in the memory section, In each section it has sufficient memory. But I can see the above mentioned functions are kind of overlapping to each other.
Working Project Images:
Non_working project images:
In those comparisons you can see the difference, These functions are kind of overlapping and it is not matching as mentioned in the map file. Currently we are seeing the hardfault handler error while running into these functions.
Can you guys help us to identify why exactly we are seeing this kind of behavior, It would be really beneficial to have a call and bevug this issue. This is kind of stopper for us for the next steps in this project for the integration.
Hi @vinaychitturi,
Maybe you can aligned the section to 64bytes in the linker file.
. = ALIGN(64);
The SAF version is compatible with certain RTD drivers, and the release notes of the drivers specify the GHS compiler and linker options. Can you check the options in your project?
Regarding the MPU, the MPU region must be aligned to its size, this is how ARM specified it. If you have 32KB region, it must be aligned to 32KB. But the size of the region can be also 8KB or 16KB.
Regards,
Daniel
Hello @danielmartynek
I look the startup code and saw what is happening and why i am seeing the overlapping issue.
Working Project:
In this project as you can see in ROM and RAM sections for the sram_no_cacheable section after .mcal_const_no_cacheable it is taking 68 bytes of gap for the ramcode_no_cacheable. But that gap is present in both RAM and ROM which is good. SO when I am trying to copy I am able to copy the whole section from flash to sram during initialization because of same gap in RAM and ROM
Non-Working Project:
In this Non-working project as you can see in ROM and RAM sections for the sram_no_cacheable section after .mcal_const_no_cacheable it is taking 4 bytes of gap for the ramcode_no_cacheable in ROM, 68 bytes in RAM. But that gap is not same in both RAM and ROM. SO when I am trying to copy Because of difference in bytes gap in RAM and ROM while copying from flash to sram during initialization it is getting overlapping.
I attached both working and non-working one . So now my question is why it is showing different memory alignment in ROM and RAM in these two projects, How can we make the ROM and RAM to have the similar alignment and similar gaps?
In the previous reply you mentioned I need to align the 32kb as per the MPU align base address, But we are not utilizing that much non_cacheable memory. In the linker file the whole no_cacehable is only 0x4d00 bytes. What kind of changes do i need to do in the MPU?
Hi @vinaychitturi,
Maybe you can aligned the section to 64bytes in the linker file.
. = ALIGN(64);
The SAF version is compatible with certain RTD drivers, and the release notes of the drivers specify the GHS compiler and linker options. Can you check the options in your project?
Regarding the MPU, the MPU region must be aligned to its size, this is how ARM specified it. If you have 32KB region, it must be aligned to 32KB. But the size of the region can be also 8KB or 16KB.
Regards,
Daniel
Thank you for the files.
I have noticed that the MPU region that starts at __RAM_NO_CACHEABLE_START has size of 32KB. That means the MPU region should be aligned to the size.
Can you try aligning it to 32KB = 0x8000?
I'm not saying this is the root cause, but it should be aligned.
Regards,
Daniel
