Clarification on Enhanced RX FIFO and Message Buffer Usage with S32K312 FlexCAN Errata

[Yogs]

Hello,

I am currently working with the FlexCAN module on the S32K312 and intend to use the Enhanced RX FIFO (ERF) for reception. While reviewing the S32K312_0P09C errata sheet, I came across the following errata related to Enhanced RX FIFO operation:

• ERR052403 – CAN frame drops in Enhanced RX FIFO when a Message Buffer (MB) is locked for more than one CAN frame time.
• ERR052438 – CAN frame may be dropped when using Enhanced RX FIFO.
• ERR052558 – Message Buffer overrun status may be cleared when reading the Enhanced RX FIFO.

The workarounds mentioned in these errata recommend avoiding the use of certain Message Buffers, specifically MB0–MB7 and MB0, 2, 10, 12, 20, 22, 30, 32, 40, 50, and 60.

I would like to clarify the following points:

1. Memory organization of Enhanced RX FIFO and Message Buffers
   • When Enhanced RX FIFO is enabled, does it internally use the same memory space as Message Buffers 0–63?
   • If not, are Enhanced RX FIFO and Message Buffers completely independent, allowing ERF to be used exclusively for reception while Message Buffers are used independently for transmission and/or reception?
2. Usage of Message Buffers with ERF enabled
   • If Enhanced RX FIFO is enabled and the Message Buffers listed in the errata are completely avoided, while the remaining Message Buffers are used only for transmission, are there any additional limitations or known issues?
   • Is the configuration of "ERF for reception + non-affected MBs for transmission" fully supported and considered safe with respect to the above errata?
3. Concurrent use of ERF and Message Buffers
   • If ERF is used for reception and only non-affected Message Buffers are configured for reception and/or transmission, can the above errata still lead to frame loss or other unexpected behavior?
4. Use of the Message Buffers listed in the errata
   • Can the affected Message Buffers (MB0, 2, 10, 12, 20, 22, 30, 32, 40, 50, and 60) be safely used for reception when ERF is enabled?
   • If they should not be used for reception, can they still be used for transmission without introducing any issues?
   • More generally, does NXP recommend avoiding these Message Buffers entirely, or are there specific restrictions depending on whether they are configured as RX or TX Message Buffers?

I would appreciate any clarification regarding the internal memory mapping between ERF and Message Buffers and the recommended configuration for reliable operation.

Thank You

[PetrS]

Hi,

see my feedback for question given... 

1.
a) No, ERF and MBs does not share same memory
b) yes, ERF can be used to receive messages and MBs for TX and/or RX operation. For sure there are few erratas for this usage

2.
a) no issues for this combination (ERF for reception + non-affected MBs for transmission)
b) yes, this config (ERF for reception + non-affected MBs for transmission) is fully supported and considered safe with respect of erratas.

3. for combination (ERF is used for reception and only non-affected MBs configured for reception and/or transmission) no frame loss and other unexpected behavior can be seen

4.
a) no, you should avoid usage on affected MBs for reception when ERF is used
b) affected MBs should not be used for TX as well
c) yes, a recommendation is avoiding usage of these affected MBs entirely when ERF is enabled

BR, Petr