Hello ,
We are currently working on FlexCAN Enhanced RX FIFO with DMA on the S32K312,
we are using the rtd v 7.0.1 and would like clarification on several observations and issues we are facing.
1. MEX Configuration Verification
Could you please verify the recommended MEX configuration for FlexCAN Enhanced RX FIFO with DMA enabled? We would like to ensure that our configuration follows the intended RTD usage model.
2. Enhanced RX FIFO + DMA Data Loss Observation
As suggested in the FlexCAN errata, the following Message Buffers are not used when Enhanced RX FIFO is enabled:
MB0–MB7, MB10, MB12, MB20, MB22, MB30, MB32, MB40, MB50, and MB60.
Our setup is as follows:
- Enhanced RX FIFO enabled
- DMA enabled
- Watermark configured to 10 entries
- DMA transfers FIFO data into a software buffer
Observed behavior:
- CAN messages are correctly received into the Enhanced RX FIFO.
- DMA transfers data successfully until the watermark level is reached.
- DMA completion interrupt is triggered.
- After this point, incoming CAN messages are not observed in the expected next FIFO location (11th FIFO entry onwards).
- Data loss and abnormal FIFO behavior are observed.
Could you please explain the expected behavior in this scenario and the likely reason for the observed message loss?
3. FlexCAN_Ip_RxFifo DMA Reconfiguration
While debugging the RTD driver, we observed that the FlexCAN_Ip_RxFifo API appears to reconfigure DMA parameters.
Specifically:
- Minor loop count appears to be configured as 16
- Transfer size appears to be 4 bytes
This results in a total transfer size of 64 bytes (or approximately 68 bytes depending on interpretation), which does not appear to match the Enhanced RX FIFO entry size described in the Reference Manual.
Could you clarify the intended operation of this API and the rationale behind these DMA settings?
4. Enhanced RX FIFO Memory Observation
Another observation during debugging is that even though DMA appears to transfer data from the FIFO into the software buffer:
- The FIFO memory region still contains older message IDs.
- The memory browser appears to show only the first Enhanced RX FIFO element.
- FIFO locations do not appear to update as expected.
A screenshot is attached for reference.
Could you explain whether this is expected behavior and how the Enhanced RX FIFO memory should be interpreted during runtime debugging?
5. Structure Size Mismatch
We also observed a discrepancy between the RTD structure and the Reference Manual.
- FlexCAN_Ip_MsgBuffType size in RTD: 78 bytes
- Enhanced RX FIFO element size according to the Reference Manual: 80 bytes
Could you clarify:
- Why this size difference exists?
- Whether any packing/alignment considerations are involved?
- Whether DMA transfers should be configured for 78 bytes or 80 bytes?
Intended Use Case
Our requirement is to use:
- Enhanced RX FIFO
- DMA-based reception
- No CPU interrupts for message reception
The intended behavior is:
- CAN message arrives in Enhanced RX FIFO.
- DMA automatically transfers the FIFO entry into a software buffer.
- No software polling or RX interrupt handling is required for normal operation.
The Message Buffers reserved by the Enhanced RX FIFO (MB0–MB7, MB10, MB12, MB20, MB22, MB30, MB32, MB40, MB50, and MB60) are intentionally avoided, while the remaining Message Buffers are used for transmission.
Request
Could you please provide:
- Any available example project demonstrating Enhanced RX FIFO with DMA operation.
- Recommended RTD configuration for this use case.
- Clarification on whether the RTD currently supports continuous Enhanced RX FIFO reception using DMA without software re-arming.
- Any bare-metal driver examples implementing Enhanced RX FIFO + DMA reception.
Thank you for your support.
