CAN PE uses peripheral clock

[chai_997128]

1. The CAN PE clock uses a peripheral clock of 60M, and CAN can communicate normally without frequency division

2. When using 12 division frequency and the clock size is 5M, communication cannot be normal.

3. Unable to run correctly when using CAN PE clock and peripheral clock 60M, propagation segment 5, synchronization segment 1 is 3, and synchronization segment 2 is 1

4. When using CAN PE clock and peripheral clock 60M, the transmission segment is 7, synchronization segment 1 is 4, and synchronization segment 2 is 1, it can operate correctly

What is the reason for this? I would like to know how to communicate normally with a 12 division frequency and a clock size of 5M

[Senlent]

Hi@chai_997128

Can you tell me which device you are using?  S32K1 or others?

[chai_997128]

Is it correct to use a peripheral clock for CAN PE clock to obtain a clock size of 5M.

[Senlent]

Hi@chai_997128

Senlent_0-1687328788850.png

I don't quiet understand, how you can set the PE clock to 5MHz? It's totally unreasonable.

[chai_997128]

chai_997128_0-1687763111320.pngchai_997128_1-1687763247973.png

Hi @Senlent When debugging this configuration, CTRL ->CLKSRC cannot be set to 1, but it can be set during single step operation.What could be the reason for this?

[Senlent]

Hi@chai_997128

from the code your provided, there is something wrong here.

Senlent_0-1687765204984.png

[chai_997128]

chai_997128_0-1687773139279.png

chai_997128_1-1687773237355.png

 Hi @Senlent I updated the CAN initialization code to this before updating the CAN_ CTRL1_ CLKSRC set. Why is this? Is it related to project engineering?

[Senlent]

Hi@chai_997128

Have you carefully read the test demo and results I gave you? Is there such a problem here? It doesn't!

[chai_997128]

The system clock is 60M

CAN can operate without frequency division using a peripheral clock

Can runs normally.

chai_997128_0-1687848034999.pngchai_997128_1-1687848040718.png

2、

60M, without frequency division

Unable to run correctly when propagation segment is 5, synchronization segment 1 is 3, and synchronization segment 2 is 1

chai_997128_2-1687848109335.png

Hi @Senlent There are two phenomena, but the settings of the propagation segment and the synchronization segment are different. One can run normally and the other cannot. Why? I don't understand. Can you explain this phenomenon?Thanks!

[Senlent]

Hi@chai_997128

The picture is not clear. Second, I see that you haven't set CTRL->CLKSRC to 1.

Don't you see any difference between these two places?

CAN0->CTRL1=0u | xx........

CAN0->CTRL1 |=0u | xx.........

[chai_997128]

I have seen the results of your presentation, and I am still looking at the reasons for my own phenomenon. thanks!

[chai_997128]

chai_997128_0-1687765573682.png

Hi @Senlent This value cannot still be set to 1, which is a strange phenomenon. All other codes are annotated, only setting CAN_ CTRL1_ CLKSRC, unable to set, running this CAN in one step_ CTRL1. The CLKSRC value can be set.

[Senlent]

Hi@chai_997128

Senlent_0-1687766184453.png

[Senlent]

Hi@chai_997128

Senlent_0-1687763827871.png

[chai_997128]

Want to have an 80% sampling point, maintain 10 Tq, clock needs to reach 5M, right? Please point out any misunderstandings, thank you.

[Senlent]

Hi@chai_997128

Can you provide your configuration ? or

Can you tell me which IDE and SDK you're using? and bitrate you need, whether CAN FD is enabled.

I can help you with some reasonable flexcan configurations.

[chai_997128]

use CAN，not use CAN FD

[chai_997128]

I did not use the SDK configuration and posted it: the system clock is configured to 60M

CAN0->CTRL1 |=(CAN_CTRL1_CLKSRC (1)); Using the system clock

CAN0->CTRL1=0u

|CAN_ CTRL1_ PRESDIV (11)/* Sys clock 5M/(11+1)=5M*/

|CAN_ CTRL1_ PSEG2 (1)/* Configure for 500 KHz bit time*/

|CAN_ CTRL1_ PSEG1 (2)/* Time quanta freq=10 time quanta x 500 KHz bit time=5MHz*/

|CAN_ CTRL1_ PROPSEG (3)/* PRESDIV+1=Fclksrc/Ftq=5 MHz/5 MHz=1*/

|CAN_ CTRL1_ RJW (1)/* PRESDIV=0*/

|CAN_ CTRL1_ SMP (1)/* PSEG2=Phase_ Seg2-1=4-1=3*/

|CAN_ CTRL1_ BOFFMSK (1)/* PSEG1=PSEG2=3*/

|CAN_ CTRL1_ BOFFREC (1); /*PROPSEG=Prop_ Seg-1=7-1=6 */* RJW: since Phase_ Seg2>=4, RJW+1=4 so RJW=3 */

/*SMP=1: use 3 bits per CAN sample*/

/*CLKsrc=0 (unchanged): Fcanclk=Fosc=8 MHz*/

/*Busoff interrupt enable*/

/*Busoff auto recovery disabled*/

I want to obtain a configuration with a sampling point of 80%.

[Senlent]

Hi@chai_997128

as your configuration,500kbps,80%,PE clock is 60MHz,works fine on myside.

Senlent_1-1687663377021.png

please check CTRL->CLKSRC is set to 1 or not

[chai_997128]

hi @Senlent  Can CAN communicate normally and is there a verification?

[Senlent]

Hi@chai_997128

I‘m using S32K146EVB board,

Senlent_1-1687672548008.png

Senlent_0-1687672504904.png

and as I know, we don't have such part number