BCTU triggering: The delay of 8.039us ADC result received & trigger channel flag generation

[nkarthik]

hi NXP Team,

I am facing the delay of 8.039us observed between the ADC result received in FIFO and trigger channel flag generation.Micro : S32K344(EVal Board). Application: Motor control.

Please find attached doc for the details.Please provide your feedback to reduce the delay time.

[Robin_Shen]

Hi

1. First, please refer to the 60.3.18 Conversion time section of S32K3XXRM, which has an example:
The total time for the three conversions = [(0 + 22 + (4×13) + 2) × 3] + 1 = 229 cycles ~= 2.862 μs

2. I see that you set the Watermark value to 4. Does the total time for the four conversions calculated based on your CORE_CLK frequency and ADC configuration match the measured results?

I see that you set the Adc Prescaler Value to 2, so the ADC controller clock is equal to half of the module clock

Best Regards,
Robin
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