Example S32K116 LPUART LIN Slave TXRX ISR S32DS.ARM.2.2

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Example S32K116 LPUART LIN Slave TXRX ISR S32DS.ARM.2.2

Example S32K116 LPUART LIN Slave TXRX ISR S32DS.ARM.2.2

*******************************************************************************************************
 Detailed Description:

 Configures the MCU to run system clock from XOSC.
 LPUART1 is set to respond to LIN header sent from master.
 Based on ID received the LPUART1 either receive frame's data and compare checksum
 or publish requested data with calculated checksum. Enhanced checksum is used.
 Interrupt is used for RX and TX operation and 2 versions of interrupt routine are available.
 VER 1 ... during response transmission receiver disabled and transmit interrupt enabled
 VER 2 ... during response transmission receiver is kept enabled

 ------------------------------------------------------------------------------
 Test HW: S32K116 EVB-Q048
 MCU: PS32K116LAM 0N96V
 Fsys: 40MHz
 Debugger: Lauterbach
 Target: internal_FLASH

******************************************************************************************************

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Hi Petr ,

You had used PTD5 as LIN sleep enable pin, but in schematic S32K116 EVB-Q048 LIN transrecevier sleep pin is pulled up to +ve .

Do we need to set PTD5 pin ?LIN sleep.PNG

Hi Yogish,

yes, if you do not need to control SLP pin then you need not to configure PTD5.

BR, Petr

Hi Petr ,

I am developing LIN Master using S32K116EVB-Q048 , is FlexIO configuration is mandatory in LIN Master ?

If yes, can you explain the how to configure FLEXIO->TIMCMP[0] register .Using SIRCDIV2 clock @8MHz for FlexIO module.

Regards ,

Yogish

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Last update:
‎05-29-2020 12:52 AM
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