u-boot ddr ram initialization

[0xEC]

hi everyone,

i am working on s32g2 series SoC. I have a53 cores which run embedded linux. i compile linux using yocto build environment which also compiles u-boot and using it on target. i have generic question that how u-boot initialize DDR ram integrated in target? in what order the u-boot functions are called i mean entry point of u-boot?

do you have any suggestion which helps me on understanding of working principles of u-boot, board initalization etc.

thanks in advance

best,

[MayanksPatel]

Hi @0xEC,

The best way to generate DDR configuration, you have to generate a new DDR configuration code based on your design.

Click the Help button in the S32DS DDR Tool for detailed help information.

Please find the attached image for your reference.

Thanks,

Mayank s Patel

[0xEC]

hi @MayaksPatel,
Thanks for reply,
actually i used s32ds to change initialization code for DDR in ATF, and i generate initialization codes and replaced the generated files with old ones which were used for 4GB DDR. but still the 2gb DDR ram version hardware not booting u-boot, it stucks at ATF. i asked other questions to change start address of U-Boot and i found some information which says SYS_TEXT_BASE and SYS_DATA_BASE must be change according to new RAM address range, but i still could not boot u-boot while initialization of DDR ram system stuck, i will try to get help from s32ds DDR tool.
best,

[MayanksPatel]

Hi @0xEC,

Before proceeding further, I need to make sure that all the basic settings are correct.

Please help share the following information:

1.Schematic diagram (including S32G DRAM port and LPDDR4 schematic diagram)

2.LPDDR4 part number and datasheet

3.Screenshot of S32DS “DDR View” page

4.Screenshots of "Init", "Diags", "operational", "shmoo" test results in the "Validation" window

Thanks,

Mayank s Patel

[0xEC · Accepted solution]

new update:

i could initialize DDR 2GB version by using following configuration in s32ds DDR config tool

which is taken from s32_lpddr4_configuration_test_app_v4_20220120_Eng.pdf documentation. 

ATF works fine and can initialize LPDDR4 2GB and can boot u-boot, u-boot is also working with no problem, but the new problem is as follows: while loading kernel it prints following logs and stucks 

i will try to solve this problem now, may be we can close this ticket if you have an idea that it is not related with DDR initialization anymore @MayanksPatel ,

Thanks for your support,

best,

[shanlan123]

HI 0xEC
have you solve this problem?

[0xEC]

hi shanlan123,

sorry i saw your comment now,

Yes i solved the problem. The problem was that the SYS_TEXT_BASE and SYS_DATA_BASE must be updated in U-Boot source according to new RAM size. And also in ATF, S32_DDR0_END value must be updated and kept sync with previous values. in my case, i shifted text and data bases from 0xffaa0000 to 0xefaa0000 and 0xffa00000 to 0xefa00000, and ddr end address from 0xffffffff to 0xefffffff. This is required because we shrink the DDR ram size and U-boot needs to be placed in DDR ram so we must shift entry point for U-boot by above changes.

Best,

[MayanksPatel]

Hi @0xEC,

I will investigate this problem and update you.

As this is a separate entity from DDR, can you please create a new ticket for this?

Thanks,

Mayank s Patel

[0xEC]

ok,
i will accept previous post as solution and create new ticket, thanks in advance,

[0xEC]

to update this thread;
I have adapted the newly generated init code from DDR RAM tool from S32DS, I debug code via lots of printfs and i got that, in ddr_utils_mmio.c file there is a function call namely get_mail(&mail) which is passed to variable with reference and inside this function, there is an register read which returns 0xFF which means training failure in source code and my ATF stucks after this failure.
Best,

[0xEC]

hi @MayanksPatel 

Thanks for reply,

for your questions,

1-) Schematic diagram of DDR Port and LPDDR4 is as follows:

DDR connection1DDR connection2DDR connection3

2)LPDDR4 part number is MT53D512M32D2, which is same chip but 2GB version used in S32G274-RDB2 board (this board has 4GB RAM whose part number is MT53D1024M32D4)

3)DDR view screen shot is:

DDR device info

4) "init", "diags", "operational" and "shmoo" test results screen shots are:

DDR_Diags_test_resultDDR_init_test_resultDDR_operational_test_resultDDR_shmoo_test

i changed density per channel parameter to 2GB and by that way all test are passed as you can see in above screen shots,

all information that you want are given, please let me know if you need any additional information,

Thanks in advance, 

Best,

[MayanksPatel]

Hi @0xEC,

It seems that there is a problem with your configuration, please try the following configuration and share the test results here.

 

[0xEC]

as i mentioned in previous reply, i changed just number of chip select parameter that you suggest to apply,

it generates init code and i adapted it to TF-A source code and it still could not initialize DDR ram.

i got more detail about the flow, the TF-A returns error code in ddr_init.c source code in execute_training(const struct ddrss_config* config) function which calls wait_firmware_execution()

and in this function there is an register read 

*mail = mmio_read_32(DDR_PHYA_APBONLY_UCTWRITEONLYSHADOW);

which returns 0xFF and in source code comment it says 0x07 is success 0xFF is failure

best,

[0xEC]

Hi @MayanksPatel,
After changing parameter that you describe, it fails even in init test, if i changed Number of Chip Selects used to 1, test passes. the result of configuration suggested by you is as follows:

best,

[MayanksPatel]

Hi @0xEC,

Ideally, u-boot doesn't initialize the DDR. DDR initialization is performed by the SPL(Secondary Program Loader).

you can refer more information from here: https://u-boot.readthedocs.io/en/stable/develop/spl.html

Hope this helps you.

Thanks,

Mayank s Patel

[0xEC]

thank you for reply,

i may have misunderstood the concept, but if u-boot does not initialize DDR, so who is responsible for this initalization. i ask this question because i have s32g274a-rdb2 board which has 4GB DDR ram and it works with yocto image that i compile which includes u-boot also, i also have 2GB DDR ram and 4GB DDR ram target custom board. in custom boards, the 2GB one does not boot even u-boot there is no response, in 4GB ram custom board u-boot is booting but after u-boot count down board reset itself. the reason that i think u-boot initialize DDR ram, because of 2GB not responding in serial console.

is there any documents which explain boot sequence of s32g274a in a53 manner? i have lots of nxp documents but none of them explain anything about booting sequence in overview.

best,

[MayanksPatel]

Hi @0xEC,

The SPL(Secondary program loader.) is the part of u-boot source code.

Please find the attached document which guides you through the boot sequence for S32G2.

Also, the current Linux BSP, starting from BSP32, all support ATF(Arm Trusted Firmware) by default, so the bootloader will first load the ATF(Arm Trusted Firmware) into the internal SRAM, and then ATF(Arm Trusted Firmware) will initialize the external DDR, and ATF will be responsible for loading the u-boot code from eMMC/SDcard.

Hope this helps you.

Thanks,

Mayank s Patel

[0xEC]

@MayanksPatelthanks for reply
I have been investigating on ATF, u-boot and linux kernel booting in yocto image, i partially understood the boot stages thank you for clearance, one thing that i wonder that, i have custom board s32g274a SoC and 2GB DRAM, even if DRAM could not be initialize ATF must be boot up right? and i should see some serial log on uart from ATF? but i could not see anything in this configuration. Do you have any suggestion that may help me?
Best,

[MayanksPatel]

Hi @0xEC,

Have you made any changes in ATF Firmware? If yes, Please share it here.

Please share the BSP version used.

Thanks,

Mayank s Patel

[0xEC]

hi @MayanksPatel,
I did not change anything in ATF fw. My BSP version is 33.0 i think this one is latest BSP in nxp yocto distribution.
Best,

[MayanksPatel]

Hi @0xEC,

Sorry for taking a long time.

The u-boot start address will be taken from the variable "CONFIG_SYS_TEXT_BASE".

This is available in the board_defconfig file. 

The following changes you need to do in the u-boot to support the custom DDR.

1. Made changes in the DTS File for DDR memory.

2.modify CONFIG_SYS_TEXT_BASE variable according to your RAM Start Address.

Hope this helps you.

Thanks,

Mayank s Patel