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Hi NXP Team,
We recently had a query from customer regarding the usage of VR5510 + S32G3 and PF8200+S32G3 as a PMIC + SOC solution.
Query: Is the timing requirements of SoC internals circuits like oscillator sections are taken in to account while choosing the delay for the release of reset to the SoC from MSOC/GSOC PMIC.
This query was raised to make sure the SoC internal circuits reach their working voltage levels before the PMICs release the reset of the SoC.
Can you guys confirm this point if this has been taken care of?
Solved! Go to Solution.
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Hello @Diwakar07 ,
Yes, you are correct. Since the PMIC releases reset after the stabilization of all it's converter's output, we satisfy this query.
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Hello @Diwakar07 ,
A quick answer to your customers query is no, the internal clock configuration of the SOC is not taken into account when choosing the delay for the release of reset of the SOC.
A more in depth answer is that it the VR5510 releases the reset pin only after all the voltage lines have the correct values, this means that the SOC does not have control over the delay for the reset release. As seen in page 15 of the VR5510 datasheet [Rev. 6 — 31 July 2023]:
With that said, there one possible delay that could be added to the reset release, via an one time programable (OTP) register. as seen in page 177 of the datasheet:
But this will depend entirely on the project requirements and design, as far as I understand it is not require to enable this 5m delay to work with the S32G3 + VR5510 setup.
One important timing that should be taken in consideration is the watchdog refresh window, in which the SOC (we recommend using the M7 cores) sends a periodic refresh through the I2C bus to the PMIC, this keeps the PMIC from resetting the SOC. The period of this window is configurable or could even be deactivated (watchdog disable). The first refresh is required even if the watchdog is disable as seen in page 66 of the datasheet:
Taking BSP41 as an example, the first WD refresh and WD disable occurs in the ATF execution which is very early in the A35 boot process, this ensures the window is not missed.
For a more detailed description of the VR5510 operation please check section 8.6 Functional state diagram in page 66 and section 22.4.4 Watchdog refresh counter, in page 69 of the datasheet.
Please let me know if this answers your customer questions.
Best regards.
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Hi @alejandro_e ,
Actually the query in simple words is will all the power rails related to internal oscillator circuits of SoC be stable before the reset release from PMIC to SoC. Since PMIC releases reset after the stabilization of all it's converter's output , Is it safe to assume that we satisfy this query?
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Hello @Diwakar07 ,
Yes, you are correct. Since the PMIC releases reset after the stabilization of all it's converter's output, we satisfy this query.