Hi there
Since both start M core(APP) and A core still no good, and refer to the attatched document,
I want to start Linux form M7_0 bootloader all lone (not include M7 APP).
I did following steps, but there was not any info output from the UART0,
Could you tell me where the problem is?
Prepare images for Cortex-A53 cores
- 1:download binaries_auto_linux_bsp33.0_s32g2_pfe.tgz and extract it
- 2:dd if=binaries_auto_linux_bsp33.0_s32g2_pfe/s32g274ardb2/fsl-image-auto-s32g274ardb2.sdcard of=/dev/sdc bs=1M status=progress && sync
- (by this, SD mode startup OK)
- 3:checkout release/bsp33.0-2020.04 and build it
- 4:checkout arm-trusted-firmware (release/bsp33.0-2.5) and buid it (`FIP_ALIGN := 64` and unset LDFLAS because I had a "aarch64-fsl-linux-ld.bfd: unrecognized option '-Wl,-O1'" error)
- 5:Build the ATF and got a fip.32 the address info as blow:
- IVT Location: SD/eMMC
- Load address: 0x342fc580
- Entry point: 0x34302000
- 6:renew fip.32
dd if=fip.s32 of=/dev/sdb skip=512 seek=512 iflag=skip_bytes oflag=seek_bytes conv=fsync,notrunc
Prepare bootloader for Cortex-A7_0 core
- 1:load Integration_Reference_Examples bootloder to EB
- 2:disable RM Eep MemDal CryptoDal Crypto plugin and releated options
- (In my Env the SDHC and HSE is still abnormal)
- 3:Bootloader(…)->Bootloader->General Software breakpoint enable uncheck
- 4:boot option like blow:
- 5:generate project and build bootloader.bin
- 6:Generate S32G Boot Image Using S32DS IVT_TOOL
- 7:Deploy the bootloader(with IVT) and fip.32 to QSPI(NOR Flash) with s32ft.exe
- bootlader 0x0000_0000
- fip.32 0x0010_0000
After above operations, set RDB2 to QSPI boot mode.
- Have you tried (at this point in time) to boot up linux (without M7 into the equation) from NOR Flash?
Yes I did and juest the yesterday's thread, the result as blow, beacuse I didn't burn the zImage to QSPI flash, U-Boot -> Linux start NG, but I think the from NOR Flash start Linux was OK.
NOTICE: BL2: v2.5(release):bsp33.0-2.5-dirty
NOTICE: BL2: Built : 08:08:26, Jan 13 2023
NOTICE: BL2: Booting BL31
U-Boot 2020.04 (Jan 13 2023 - 16:06:18 +0800)
CPU: NXP S32G274A rev. 2.0
Model: NXP S32G274A-RDB2
DRAM: 3.5 GiB
MMC: FSL_SDHC: 0
Loading Environment from SPI Flash... SF: Detected mx25uw51245g with page size 256 Bytes, erase size 64 KiB, total 64 MiB
*** Warning - bad CRC, using default environment
Using external clock for PCIe0, CRNS
Configuring PCIe0 as RootComplex(x2)
Using external clock for PCIe1, CRNS
Frequency 125Mhz configured for PCIe1
Configuring PCIe1 as SGMII(x2) [XPCS0 2.5G, XPCS1 OFF]
Setting PCI Device and Vendor IDs to 0x4002:0x1957
PCIe0: Failed to get link up
Pcie0: LINK_DBG_1: 0x00000000, LINK_DBG_2: 0x00000800 (expected 0x000000d1)
DEBUG_R0: 0x00189900, DEBUG_R1: 0x08200000
PCI: Failed autoconfig bar 20
PCI: Failed autoconfig bar 24
PCIe1: Not configuring PCIe, PHY not configured
In: serial@401c8000
Out: serial@401c8000
Err: serial@401c8000
Board revision: RDB2/GLDBOX Revision D
Net: EQOS phy: rgmii @ 1
Warning: eth_eqos (eth0) using random MAC address - 12:e8:6d:ee:63:42
eth0: eth_eqos PFE: emac0: sgmii emac1: none emac2: rgmii
## No elf image at address 0xffdc92f8
PFEng firmware file '<NULL>@0x03000000:<NULL>' loading failed: -22
Hit any key to stop autoboot: 0
## No elf image at address 0xffdc9048
PFEng firmware file '<NULL>@0x03000000:<NULL>' loading failed: -22
PFE: emac0: sgmii emac1: none emac2: rgmii
pfeng_cfg_mode_enable: Invalid PFE device
Booting from flash...
device 0 offset 0x1f0000, size 0xe00000
SF: 14680064 bytes @ 0x1f0000 Read: OK
device 0 offset 0xff0000, size 0x100000
SF: 1048576 bytes @ 0xff0000 Read: OK
device 0 offset 0x10f0000, size 0x2000000
SF: 33554432 bytes @ 0x10f0000 Read: OK
Bad Linux ARM64 Image magic!
=>
=>
- From the first point you mentioned "...and fip.32-sdcard to QSPI Flash, the Linux can start normally in QSPI mode." and also "...I hexdumped the fip.32-sdcard and you can the IVT image is on the 0x1000." we understand you tried this option, but it is not explicitly mentioned.
- We suspect you got your platform to boot up from the SD (not QSPI), which is expected from the steps you mentioned (and files you used).
Maybe I didn't explain my process in detail enough, in my boot sequence, The used IVT is included in M7_ 0_ Bootloader, not fip, and in M7_ 0_ Bootloader.bin the offset of the IVT image is 0x0.
(means that the fip.32 was called by M7_0 bootloader, not by BOOTROOM)
I don't know if you have read the attachment I added [Enabling Multicore Application on S32G2 .pdf]
the deployment as blow:
As I said in before thread, the actual boot flow is:
- BOOTROM -> M-core bootloader(with IVT in NOR Flash) -> M-core APP
|-------A-core FIP(in NOR Flash but load and start by M-core bootloader) -> A-Core U-Boot(in SD-Card)->A-Core Linux(in SD-Card)
Therefore, the FIP image must be in SD-Card mode because it needs to read U-boot from SD card.
Please focus on document I was attached [Enabling Multicore Application on S32G2 .pdf]
I refer to this document in depth and have the following differences from it:
1: don't use IPC(both Linux and MCAL)
2:use Uart_TS_T40D11M30I2R0(RTD_4.4_3.0.2) replace to IPCF_Example
3:disable crypto and SDHC on bootloader
So now I'm puzzled why the UART of M-core can start normally, but the U-Boot and Linux of A-core can't start(maybe start OK but can't output to UART...).
Is it the reason that my bootloader does not contain crypto and SDHC?
In addition, I debugged the bootloader and found that FIP was loaded and executed normally without any error
bootloader.c
- main()
- Bl_Run()
- Bl_BootApplications()
- Bl_LoadApplication()
- Bl_FetchApplication()
- Bl_LoadAndAuthFromQspi()
- Bl_StartDmaTransfer()
// Fetch application image and copy to RAM OK
- Bl_StartAllApplications()
- Bl_StartApplication()
// run FIP image(BL2) OK
- Bl_StartApplicationOnCurrentCore()
// run UART sample OK
- update CST 2023/01/14 21:43
Just refer to the [Enabling Multicore Application on S32G2 .pdf], I rebuild the bootloader with SDHC and HSE
So, for now, the only difference from the document is that I use UART instead of IPCF to verify M7's actions.
But still work abnormal.
To facilitate understanding, I clean up my boot flow as blow:
