S32G399 SGMII interface driver issue

[LONGGANGSU]

Hello, I have a question. Currently, I'm adjusting the SERDES interface of S32G. Two lanes of SERDES1 are connected to one PHY (VSC8572). The problem I'm encountering is that the network port is unstable. I'm now testing the SGMII eye diagram signal. The eye low of the TX signal from S32G399 (AC capacitor near the PHY side) is 150mV. The eye low of the RX signal from S32G399 (AC capacitor near the CPU side) is 328mV.

RX:

LONGGANGSU_0-1756129649980.png

TX:

LONGGANGSU_1-1756129661003.png

[LONGGANGSU]

Could you please tell me what methods can be used to enhance the CPU's driving capability?

[alejandro_e]

Hello @LONGGANGSU,

Thanks for contacting us. Regarding your question, please check the following document S32G3 - Hardware Design Guidelines User Guide, in particular sections:

• 10.2 SerDes communication
  • 10.2.2 SGMII recommendation
  • 10.2.4 PCIe/SGMII design recommendations
• 13.3 High-speed routing recommendations

You can also check the RDB3 schematics as reference for your design. 

Please note that the signal integrity topic is outside my area of expertise, so I may not be able to help you much. However I will do my best to support you.

when you mention "the network port is unstable", can you clarify what test have you perform to arrive to that conclusion?

Thanks

[LONGGANGSU]

LONGGANGSU_0-1756173316515.png

I followed the hardware design manual to do the following:
1. The clock was set at 125 MHz for Serdes1, and the PHY was also set at 125 MHz.
2. The AC coupling capacitor was designed to be 0.1uF and placed close to the receiving end.
3. The PCIE1_REXT pin was designed with a 100-ohm resistor connected to ground.

The problem I am currently facing:

When the SGMII connection fails, by querying the PHY vsc8572's Mac SerDes PCS status through MDIO, the result is = 0x0400, indicating that the MAC is not detected.

LONGGANGSU_1-1756173587995.png

[alejandro_e]

Hello @LONGGANGSU,

Thanks for the information. What I am undertanding is that no SGMII operation can be done, this is, you have connected your PHY to another device with an ethernet cable and you cannot get connection, is that correct?

Regarding the register, you mentioned that you get 0x0400, which has only the tenth bit ON, however, from the screenshot of the datasheet, I see that bit 10 is reserved, do you have any other indicator of the problem?

I would also recommend to contact your PHYs vendor in parallel for better support.

Thanks in advance