S32G3 bsp41 XPCS are in reset and init failed on the customized board

[XD]

Hi,

I received our customized board and used BSP41 to boot it up. The board has some modifications to GMAC and PFE configurations, which are set as follows: SGMII, SGMII, SGMII, and RGMII, respectively.

For the SERDES configuration, I used mode 1 for SERDES0 and mode 3 for SERDES1. The hwconfig was set to:
serdes0:mode=pcie&xpcs0,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=1G;xpcs1_1:speed=1G.

In this setup:

GMAC and PFE2 do not have external PHYs.
PFE0 and PFE1 are connected to external PHYs.

I made the corresponding changes in TF-A device tree. However, when U-Boot initializes, I noticed that both XPCS0 and XPCS1 are in reset, init failed. I’ve attached a screenshot for reference. Could you please share any insights or suggestions on this issue? 

The PFE0 and PFE1 external PHY has not power enabled yet, so the PHY was not found error is expected.

Thanks,

XD

Loading Environment from SPIFlash... SF: Detected mx25uw51245g with page size 256 Bytes, erase size 64 KiB, total 64 MiB
OK
Failed to configure XPCS1_0
Failed to update XPCS0 for SerDes1
Failed to configure XPCS1_1
Failed to update XPCS1 for SerDes1
s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: XPCS0 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
pci_s32cc pcie@40400000: Failed to get PHY 'serdes_lane0'
In:    serial@401c8000
Out:   serial@401c8000
Err:   serial@401c8000
Board revision: Revision Unknown: (0x496)
Net:   s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: XPCS0 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
eth_eqos ethernet@4033c000: Failed to get 'gmac_xpcs' PHY
eth_eqos ethernet@4033c000: XPCS init failed. Check hwconfig. (err=-19)
Enable protocol@14 failed
clk_enable(clk_rx) failed: -71
eth_eqos ethernet@4033c000: Failed to start clocks. Check XPCS configuration (err=-71)
eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 block was initialized
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 7)
s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: XPCS1 power good timeout
s32cc_serdes_phy serdes@44180000: XPCS0 power good timeout
s32cc_serdes_phy serdes@44180000: XPCS1 is in reset
s32cc_serdes_phy serdes@44180000: XPCS init failed
pfeng_netif pfe0: Failed to get 'emac0_xpcs' PHY
Could not get PHY for pfeng-mdio-0: addr 0
pfeng_netif pfe0: PHY device not found
pfeng_netif pfe0: PHY config failed (-19)
s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
No space for a new XPCS instance
s32cc_serdes_phy serdes@44180000: XPCS init failed
pfeng_netif pfe1: Failed to get 'emac1_xpcs' PHY
Could not get PHY for pfeng-mdio-1: addr 0
pfeng_netif pfe1: PHY device not found
pfeng_netif pfe1: PHY config failed (-19)

[chenyin_h]

Hello， @XD 

OK, thanks for your detailed clarification, when finished the mdio debugging with PHY well connected, if still issues on serdes configuration, contact us any time, we could continue the discussion on it.

Furthermore, for such kinds of network bring up issues, I suggest sharing the related schematic with us for further investigation also, since it may not be convenient to share via the community, you may create private support case later if needed.

BR

Chenyin

[XD]

Hi @chenyin_h ,

Thank you very much for your help.

We made some modifications and got PFE0 working. Additionally, we added an oscillator to generate a 100MHz clock for SerDes0, and it seems that this SerDes is now able to come out of reset.

Thanks,

XD

[chenyin_h]

Hello, @XD 

You are welcome.

From the log, seems the serdes0 still init failed, while serdes1 looks fine after applying for the changes, is it right?

BR

Chenyin

[XD]

Hi @chenyin_h ,

Yes, the same clock=int were applied to both serdes, only the serdes1 has not init failure any more. However, I am still working on the mdio access external PHY issues on serdes1 pfe0 and pfe1. So cannot verify these two interfaces are fully working until solve the PHY issues.

Thanks,

XD

[chenyin_h]

Hello, @XD 

Thanks for your reply.

Yes, from the current log, seems the serdes1 status is correct, may I know what kind of modification you had made?

For serdes0, the log shows it is not correct, by reviewing the code, would you mind trying the following modifications on u-boot 

diff --git a/drivers/net/pcs/nxp-s32cc-xpcs.c b/drivers/net/pcs/nxp-s32cc-xpcs.c
index 38acad9fe7..5f643b93a3 100644
--- a/drivers/net/pcs/nxp-s32cc-xpcs.c
+++ b/drivers/net/pcs/nxp-s32cc-xpcs.c
@@ -519,7 +519,7 @@ static bool is_not_in_reset(struct s32cc_xpcs *xpcs)
{
u32 val;

- val = XPCS_READ(xpcs, SR_MII_CTRL);
+ val = XPCS_READ(xpcs, VR_MII_DIG_CTRL1);

return !(val & SR_RST);
}

Thanks for sharing the new logs.

BR

Chenyin

[XD]

Hi @chenyin_h ,

Thank you for your reply.

I did not change anything on code, just modified the hwconfig, changed both serdes "clock=ext" to "clock=int" 

the previous hwconfig,

serdes0:mode=pcie&xpcs0,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=1G;xpcs1_1:speed=1G

current hwconfig,

serdes0:mode=pcie&xpcs0,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs1_0:speed=1G;xpcs1_1:speed=1G

and here is the new log after applying the nxp-s32cc-xpcs.c change. However, I don't think that function was executed. I have printf in the code and patch it to bb file.

=> setenv hwconfig "serdes0:mode=pcie&xpcs0,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G,an=0"
=> save
Saving Environment to SPIFlash... Erasing SPI flash...Writing to SPI flash...done
OK
=> reset
resetting ...
ERROR:   read error from device: 0x34330408 register: ERROR:   Failed to disable VR5510 watchdog
NOTICE:  Reset status: Destructive Reset (RUN)
NOTICE:  BL2: v2.10.0   (release):bsp41.0-2.10-dirty
NOTICE:  BL2: Built : 09:32:10, May 27 2024
NOTICE:  BL2: Booting BL31


U-Boot 2022.04+g4744d0e2c8+p0 (May 27 2024 - 09:33:20 +0000)

SoC:   NXP S32G399A rev. 1.1
CPU:   ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM:  3.5 GiB
Core:  312 devices, 24 uclasses, devicetree: board
MMC:   FSL_SDHC: 0
Loading Environment from SPIFlash... SF: Detected mx25uw51245g with page size 256 Bytes, erase size 64 KiB, total 64 MiB
OK
s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: XPCS0 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
pci_s32cc pcie@40400000: Failed to get PHY 'serdes_lane0'
In:    serial@401c8000
Out:   serial@401c8000
Err:   serial@401c8000
Board revision: Revision Unknown: (0x496)
Net:   s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: XPCS0 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
eth_eqos ethernet@4033c000: Failed to get 'gmac_xpcs' PHY
eth_eqos ethernet@4033c000: XPCS init failed. Check hwconfig. (err=-19)
Enable protocol@14 failed
clk_enable(clk_rx) failed: -71
eth_eqos ethernet@4033c000: Failed to start clocks. Check XPCS configuration (err=-71)
eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 block was initialized
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 7)
s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS1
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS0
, eth1: pfe0, eth2: pfe1, eth3: pfe2
Hit any key to stop autoboot:  0 




git diff recipes-bsp/u-boot/u-boot-s32_2022.04.bb
diff --git a/recipes-bsp/u-boot/u-boot-s32_2022.04.bb b/recipes-bsp/u-boot/u-boot-s32_2022.04.bb
index aeb44d20..4ebf970c 100644
--- a/recipes-bsp/u-boot/u-boot-s32_2022.04.bb
+++ b/recipes-bsp/u-boot/u-boot-s32_2022.04.bb
@@ -8,4 +8,5 @@ LIC_FILES_CHKSUM += " \
 # Support for generating default environment
 SRC_URI += " \
     file://0001-env-Add-Makefile-rule-to-generate-default-environment-${PV}.patch \
+    file://0001-nxp-changes.patch \
 "
git diff recipes-bsp/u-boot/u-boot-s32_2022.04.bb
diff --git a/recipes-bsp/u-boot/u-boot-s32_2022.04.bb b/recipes-bsp/u-boot/u-boot-s32_2022.04.bb
index aeb44d20..4ebf970c 100644
--- a/recipes-bsp/u-boot/u-boot-s32_2022.04.bb
+++ b/recipes-bsp/u-boot/u-boot-s32_2022.04.bb
@@ -8,4 +8,5 @@ LIC_FILES_CHKSUM += " \
 # Support for generating default environment
 SRC_URI += " \
     file://0001-env-Add-Makefile-rule-to-generate-default-environment-${PV}.patch \
+    file://0001-nxp-changes.patch \
 "

Thanks,

XD

[XD]

Hi @chenyin_h ,

The read VR_MII_DIG_CTRL1 is working, I attached the new output.

Thanks,

XD

U-Boot 2022.04+g4744d0e2c8+p0 (May 27 2024 - 09:33:20 +0000)

SoC:   NXP S32G399A rev. 1.1
CPU:   ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM:  3.5 GiB
Core:  312 devices, 24 uclasses, devicetree: board
MMC:   FSL_SDHC: 0
Loading Environment from SPIFlash... SF: Detected mx25uw51245g with page size 256 Bytes, erase size 64 KiB, total 64 MiB
OK
s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
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read VR_MII_DIG_CTRL1
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s32cc_serdes_phy serdes@40480000: XPCS0 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
pci_s32cc pcie@40400000: Failed to get PHY 'serdes_lane0'
In:    serial@401c8000
Out:   serial@401c8000
Err:   serial@401c8000
Board revision: Revision Unknown: (0x495)
Net:   s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
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read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
s32cc_serdes_phy serdes@40480000: XPCS0 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
eth_eqos ethernet@4033c000: Failed to get 'gmac_xpcs' PHY
eth_eqos ethernet@4033c000: XPCS init failed. Check hwconfig. (err=-19)
Enable protocol@14 failed
clk_enable(clk_rx) failed: -71
eth_eqos ethernet@4033c000: Failed to start clocks. Check XPCS configuration (err=-71)
eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 block was initialized
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 7)
s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
read VR_MII_DIG_CTRL1
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS1
read VR_MII_DIG_CTRL1
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS0
, eth1: pfe0, eth2: pfe1, eth3: pfe2
Hit any key to stop autoboot:  0 
=> pring hwconfig
Unknown command 'pring' - try 'help'
=> print hwconfig
hwconfig=serdes0:mode=pcie&xpcs0,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=125;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G,an=0
=> 
                                                                                                                  

[chenyin_h]

Hello, @XD 

You are welcome.

Currently, seems the bug I noticed is related with mode 5 only.

BR

Chenyin

[XD]

Hi @chenyin_h ,

Thank you for the confirmation.

Currently, I am using BSP41 and have configured hwconfig to set both SerDes0 and SerDes1 to use the internal reference clock:

"serdes0:mode=pcie&xpcs0,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs1_0:speed=1G;xpcs1_1:speed=1G"

From the output (attached below), it appears that xpcs0 is still in reset, while xpcs1 shows some improvement. Does this indicate that xpcs1 is now functioning correctly, but the internal reference clock is not working for xpcs0? Is my understanding correct?

Thanks,

XD

=> setenv hwconfig "serdes0:mode=pcie&xpcs0,clock=int,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=int,fmhz=100;xpcs1_0:speed=1G;xpcs1_1:speed=1G"
=> save
Saving Environment to SPIFlash... Erasing SPI flash...Writing to SPI flash...done
OK
=> reset
resetting ...
ERROR:   read error from device: 0x34330408 register: ERROR:   Failed to disable VR5510 watchdog
NOTICE:  Reset status: Destructive Reset (RUN)
NOTICE:  BL2: v2.10.0   (release):bsp41.0-2.10-dirty
NOTICE:  BL2: Built : 09:32:10, May 27 2024
NOTICE:  BL2: Booting BL31


U-Boot 2022.04+g4744d0e2c8+p0 (May 27 2024 - 09:33:20 +0000)

SoC:   NXP S32G399A rev. 1.1
CPU:   ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM:  3.5 GiB
Core:  312 devices, 24 uclasses, devicetree: board
MMC:   FSL_SDHC: 0
Loading Environment from SPIFlash... SF: Detected mx25uw51245g with page size 256 Bytes, erase size 64 KiB, total 64 MiB
OK
Failed to configure XPCS1_0
Failed to update XPCS0 for SerDes1
Failed to configure XPCS1_1
Failed to update XPCS1 for SerDes1
s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: XPCS0 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
pci_s32cc pcie@40400000: Failed to get PHY 'serdes_lane0'
In:    serial@401c8000
Out:   serial@401c8000
Err:   serial@401c8000
Board revision: Revision Unknown: (0x496)
Net:   s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: XPCS0 is in reset
s32cc_serdes_phy serdes@40480000: XPCS init failed
eth_eqos ethernet@4033c000: Failed to get 'gmac_xpcs' PHY
eth_eqos ethernet@4033c000: XPCS init failed. Check hwconfig. (err=-19)
Enable protocol@14 failed
clk_enable(clk_rx) failed: -71
eth_eqos ethernet@4033c000: Failed to start clocks. Check XPCS configuration (err=-71)
eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 block was initialized
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 7)
s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS1
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS0
Could not get PHY for pfeng-mdio-0: addr 0
pfeng_netif pfe0: PHY device not found
pfeng_netif pfe0: PHY config failed (-19)
Could not get PHY for pfeng-mdio-1: addr 0
pfeng_netif pfe1: PHY device not found
pfeng_netif pfe1: PHY config failed (-19)
, eth3: pfe2
Hit any key to stop autoboot:  0 

[chenyin_h]

Hello, @XD 

Thanks for your reply.
I have checked the code, and found that in BSP41 there seems bug existed for Serdes1 Mode5 in U-boot. 

May I know if it is convenient for use to try it on BSP42?

BR

Chenyin 

[XD]

Hi @chenyin_h ,

Thank you for looking into this issue.

Based on our hardware routing, I need to use Mode 1 on SerDes0 and Mode 3 on SerDes1. Could you confirm if the bug only affects Mode 5 on SerDes1, or if it occurs with every internal reference clock? If Mode 1 and Mode 3 are unaffected, I can continue using BSP41.

Otherwise, I may need to merge my changes into BSP42, as this hardware version does not have an external clock.

Thanks,

XD

[chenyin_h]

Hello, @XD 

I remember that the "clock=int" should be available, and according to the UM, the following hwconfig could be seen:

Would you please help to share more logs for the setting issue you met?  (also BSP version used)

BR

Chenyin

[XD]

Hi @chenyin_h ,

Thank you for your reply.

We are using bsp41, here is the log after changing to the new hwconfig.

Thanks,

XD

U-Boot 2022.04+g4744d0e2c8+p0 (May 27 2024 - 09:33:20 +0000)

SoC:   NXP S32G399A rev. 1.1
CPU:   ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM:  3.5 GiB
Core:  312 devices, 24 uclasses, devicetree: board
MMC:   FSL_SDHC: 0
Loading Environment from SPIFlash... SF: Detected mx25uw51245g with page size 256 Bytes, erase size 64 KiB, total 64 MiB
OK
Disabling XPCS1_0
Failed to configure XPCS1_1
Failed to update XPCS1 for SerDes1
s32cc_serdes_phy serdes@40480000: Using mode 0 for SerDes subsystem
pci_s32cc pcie@40400000: DBI R/W is not being enabled
pci_s32cc pcie@40400000: PCI Device and Vendor IDs could not be set
pci_s32cc pcie@40400000: DBI R/W is not being enabled
s32cc_serdes_phy serdes@40480000: Failed to lock PCIe phy
s32cc_serdes_phy serdes@40480000: PHY: Failed to power on serdes@40480000: -110.
pci_s32cc pcie@40400000: Failed to power on PHY 'serdes_lane0'
pci_s32cc pcie@40400000: Failed to set PCIe host settings
s32cc_serdes_phy serdes@44180000: Using mode 5 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: XPCS INIT failed
s32cc_serdes_phy serdes@44180000: Switch to PLLB failed
s32cc_serdes_phy serdes@44180000: Failed to prepare SerDes for PCIE & XPCS @ 2G5 mode
s32cc_serdes_phy serdes@44180000: XPCS init failed
pci_s32cc pcie@44100000: Failed to get PHY 'serdes_lane0'
In:    serial@401c8000
Out:   serial@401c8000
Err:   serial@401c8000
Board revision: Revision Unknown: (0x495)
Net:   s32cc_serdes_phy serdes@40480000: Couldn't translate XPCS to lane
eth_eqos ethernet@4033c000: Failed to get 'gmac_xpcs' PHY
eth_eqos ethernet@4033c000: XPCS init failed. Check hwconfig. (err=-22)
Enable protocol@14 failed
clk_enable(clk_rx) failed: -71
eth_eqos ethernet@4033c000: Failed to start clocks. Check XPCS configuration (err=-71)
eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 not used, skipped
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 6)
s32cc_serdes_phy serdes@44180000: Using mode 5 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: XPCS INIT failed
s32cc_serdes_phy serdes@44180000: Switch to PLLB failed
s32cc_serdes_phy serdes@44180000: Failed to prepare SerDes for PCIE & XPCS @ 2G5 mode
s32cc_serdes_phy serdes@44180000: XPCS init failed
pfeng_netif pfe1: Failed to get 'emac1_xpcs' PHY
Could not get PHY for pfeng-mdio-1: addr 0
pfeng_netif pfe1: PHY device not found
pfeng_netif pfe1: PHY config failed (-19)
, eth3: pfe2
Hit any key to stop autoboot:  0 
=> print hwconfig
hwconfig=serdes0:mode=pcie,clock=ext;pcie0:mode=rc;serdes1:mode=pcie&xpcs1,clock=int,fmhz=100;pcie1:mode=rc;xpcs1_1:speed=2G5
=> 

[chenyin_h · Accepted solution]

Hello, @XD 

Thanks for @jiajun_cheng 's kindly input, yes, from the log, it seems like the case we ever supported

You mentioned that both PCIE0_CLK_P/N and PCIE1_CLK_P/N are grounded, then you may have to use the internal clock to driver.

BR

Chenyin

[XD]

Hi @chenyin_h ,

Thank you for your input.

How can I make the change to use the internal reference clock? I tried changing the hwconfig from clock=ext to clock=int, but it didn’t help. It seems like the U-Boot code only recognizes the ext keyword. Maybe I missed something. Do you have any suggestions?

Thanks,

XD

[jiajun_cheng]

Hi, @XD :

I have also been debugging our custom board recently, although the interfaces used are slightly different, I only used (gmac0 & pfe2) I also encountered the same log.

In our hardware, it was caused by the routing and PCIE0_CLK_P. So I suggest you look at the hardware reasons first:

1. Is the serdes clock 125/100mhz
2. Is the power supply normal

[XD]

Hi @jiajun_cheng ,

Thank you for you suggestions.

According to the schematics, both PCIE0_CLK_P/N and PCIE1_CLK_P/N are grounded. Does the XPCS share the same clock as the PCIE? If so, is it possible to use the internal reference clock to feed into the SERDES instead?

Thanks,

XD