S32G3 RDB3 uboot hwconfig for example 4 in bsp41

[XD]

Hi,

I am trying to configure GMAC0, PFE0/1/2 to SGMII, SGMII, and RGMII, respectively, as described in Example 4 of the Ethernet Enablement User Guide. In that document, the hwconfig is specified as:

setenv hwconfig "pcie0:mode=sgmii,clock=ext,fmhz=100,xpcs_mode=0;pcie1:mode=sgmii,clock=ext,fmhz=125,xpcs_mode=both"

However, it seems that the format has changed in BSP 41. I made the necessary changes according to the BSP 41 User Guide and got the following:

=> print hwconfig
hwconfig=serdes0:mode=pcie&xpcs0,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=1G;xpcs1_1:speed=1G

This corresponds to serdes 0 in mode 1 and serdes 1 in mode 3.

But, according to the BSP 41 User Guide, mode 1 is only mentioned for serdes 1. Could you please clarify how I should set the hwconfig in my case to match the configuration I need?

Thanks,

XD

[alejandro_e]

Hello @XD,

Thanks for the detailed description of your problem.  My understanding is that you want to achieve the following configuration [page 2760, S32G3 Reference Manual, Rev. 4, 02/2024]:

Which will output GMAC0, PFE_EMAC0 and PFE_EMAC1.

As you mentioned, the table 7 in the BSP41 manual only mentions Serdes 1 in mode 1, this might be an error in the documentation, Since in the next subsection 7.2.2.1 Example configurations [page 50 and 51, Linux BSP 41.0 User Manual for S32G3 platforms] you can see mode one is also configured for SerDes 0:

I will have to confirm with the internal team if it is an error.

and you can also see SerDes 1 in mode 3:

Following these two examples the correct configuration is:

serdes0:mode=pcie&xpcs0,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G

As you can see, with this configuration you get Serdes 0 (serdes@40480000) in mode 1 and Serdes 1 (serdes@44180000) in mode 3:

U-Boot 2022.04+g4744d0e2c8+p0 (May 27 2024 - 09:33:20 +0000)

SoC:   NXP S32G399A rev. 1.1
CPU:   ARM Cortex-A53 r0p4 @ max 1300 MHz
Model: NXP S32G399A-RDB3
DRAM:  3.5 GiB
Core:  306 devices, 25 uclasses, devicetree: board
MMC:   FSL_SDHC: 0
Loading Environment from MMC... OK
s32cc_serdes_phy serdes@40480000: Using mode 1 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS0
pci_s32cc pcie@40400000: Configuring as RootComplex
pci_s32cc pcie@40400000: Failed to get link up
In:    serial@401c8000
Out:   serial@401c8000
Err:   serial@401c8000
Board revision: RDB3 Revision F
PCIe:   BusDevFun       VendorId   DeviceId   Device Class       Sub-Class
__________________________________________________________________________
pcie@40400000 RootComplex
|   `-- 01:00.00        0x1957     0x4300     Bridge device           0x04
Net:   eth0: ethernet@4033c000
Found PFE version 0x0101 (S32G3)
pfeng pfeng-base: Uploading CLASS firmware
pfeng pfeng-base: EMAC0 block was initialized
pfeng pfeng-base: EMAC1 block was initialized
pfeng pfeng-base: EMAC2 block was initialized
pfeng pfeng-base: Enabling the CLASS block
pfeng pfeng-base: PFE Platform started successfully (mask: 7)
s32cc_serdes_phy serdes@44180000: Using mode 3 for SerDes subsystem
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS1
s32cc_serdes_phy serdes@44180000: Unstable RX detected on XPCS0
, eth1: pfe0, eth2: pfe1, eth3: pfe2
Hit any key to stop autoboot:  0
=>
=> printenv hwconfig
hwconfig=serdes0:mode=pcie&xpcs0,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_0:speed=1G,an=0;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=1G,an=0;xpcs1_1:speed=1G
=> xpcs list
Registered XPCS instances:

| ID | SerDes instance | XPCS |
|  0 | serdes@40480000 |    0 |
|  1 | serdes@44180000 |    1 |
|  2 | serdes@44180000 |    0 |
=>

In the mentioned section you will also see how to configure the switch 17 and switch 8 to obtain the desired result in your RDB3.

For more details about the switches configuration you can check the RDB3 schematics [S32G-VNP-RDB3-DESIGN-FILES] in page 6:

As you are probably aware for this configuration you will need to reconfigure the SJA110, for which you need the SJA1110 SDK and it requires to sign an NDA. For this I can recommend contacting your FAE/DFAE/NXP representative so he/she may help you enabling this product in you account.

Let me know if this information solved your question. 

[alejandro_e]

Hello @XD,

I have confirmed that table 7 in page 49 of the BSP41 user manual is incorrect. SerDes 0 can be configured in mode 1 as described in the examples I mentioned.

Best regards, 

Alejandro 

[XD]

Hi @alejandro_e ,

Thank you for your prompt response and clarification.

I have a follow-up question. In the Ethernet Enablement User Guide, Example 4 shows GMAC0 using SerDes0 Lane 0. However, in our case, the hwconfig sets GMAC0 to SerDes0 Lane 1 (which I believe also aligns with Example 4). Could you clarify which lane GMAC0 should use in this setup?

Additionally, if we use a different configuration, are there any physical changes we need to make? We are currently in the custom board design stage and would like to confirm if this lane change is solely a software configuration or if hardware modifications, such as rerouting connections, are required. Our board does not have a DIP switch.

Thanks,

XD

[alejandro_e]

Hello @XD,

 Following the reference manual, you can configure GMAC0 in either lane 0 or 1 [page 2760, S32G3 Reference Manual, Rev. 4, 02/2024]:

Be also aware of the XPCS (Physical Coding Sublayer) mapping, in the same page of the reference manual:

About the routing, yes there could be pins changes depending on the software configuration, to avoid confusion in the interpretation please check the schematics, [S32G-VNP-RDB3-DESIGN-FILES] in page 6 you can see the block diagram and a table for the configuration,  knowing the dip switch configuration and tracking back the muxes to the S32G you can :

For example., PFE_MAC2 can be in two ping groups:

Let me know if this information answers your questions.

[XD]

Hi @alejandro_e ,

Thank you for the detailed explanation.

If we select mode 1 on SERDES0, GMAC0 will be mapped to PHY Lane 1. Does this mean the Ethernet MAC mapping to the XPCS table will change, placing GMAC0 on SERDES0 and XPCS1? I want to confirm that our hardware design correctly connects GMAC0 to the appropriate PCIe lanes in this mode 1 configuration.

Thanks,

XD

[alejandro_e · Accepted solution]

Hello @XD,

Sorry for the late response I was doing some investigation, to answer your questions, in MODE1, this means using GMAC in SGMII in PHY lane 1, the output will be in the following pins:

Let me know if this information solves all your questions and if the description matches the behavior in your HW.