S32G3 QSpi NorFlash

[jiajun]

Hi,

I was looking at the AN13563 document and saw that"S32G does not have internal flash",

but in "S32G3 Reference Manual" annexes "S32G3_memory_map.xlsx",I see that the address from 0x0-0x1fff ffff is the QSPI AHB Buffer

So I've got a few questions for you.

1. Is this QSPI AHB Buffer referring to the external 64M size flash?

2. So how does this portion of memory migrate to ram after power up and how is it mapped in ram, also please let me know,or maybe we should go to that document.

3. When I need to perform an erasure and write action on an external flash, how do I go about it?

Please guide me,because the flash in the previous project was inside the chip.

MY environments:

S32G-VNP-RBD3, S32DS 3.5 

S32G-VNP-RDB3 S32G3 

[alejandro_e · Accepted solution]

Hello @jiajun , Thanks for contacting NXP support. Here is the information I was able to find for all your questions:

Q1. Is this QSPI AHB Buffer referring to the external 64M size flash?

A1. This memory region, from 0x00_0000_0000 to 0x00_1FFF_FFFF, is not the 64M flash directly, it is the AHB buffer, that works like an intermediary between the real flash and the processors reading it. There is a direct mapping between the addresses in ram buffer and the flash device.

You can read more about this in the following sections of the reference manual [S32G3 Reference Manual, Rev. 4, 02/2024]:

• 39.5 Flash memory mapped AMBA bus
  • 39.5.1 AHB bus access read considerations
  • 39.5.5.2 AHB RX Data Buffer Register (ARDB0 - ARDB127)
  •  
• 39.6.2.8 Flash memory read

Q2. So how does this portion of memory migrate to ram after power up and how is it mapped in ram, also please let me know, or maybe we should go to that document.

A2. This migration of data occurs during the boot process, you can find more info about it in the following documents:

• Reference manual [S32G3 Reference Manual, Rev. 4, 02/2024]:
  • 31.7 Boot flow
  • 31.7.1 Boot flow phases
  • 31.7.2 Boot flow diagram
• AN13456 - S32G3 Boot Process [Rev. 1, 02/2023]
  • 6. BootROM
  • 7.2. QSPI Boot

You can also check the application note “AN13750 - Enabling Multicore App” [Rev. 0, 11/2022] for the RDB2, although it may no work exactly like that in the RDB3, it can give you a good idea on how the mapping of the ram and the flash is done. As you will see in that App note, the exact mapping will is related your linker file.

Q3. When I need to perform an erasure and write action on an external flash, how do I go about it?

A3. There are two ways to do it:

one is with the flash tool, you can also check the steps in the “AN13750 - Enabling Multicore App”, in section “6. Deployment on s32g-vnp-rdb2”, step 8.

If you want to do it during runtime you can check the RTD example “Qspi_Ip_Example_S32G399A_M7”, there you can see how to init, erase, write and read the QSPI flash. You can also go inside the functions definitions for more details about the registers usage.

Please let us know if this information answers all your questions.