Hi,
We have a custom S32G399A board that uses PFE0 in RGMII mode to a gigabit transceiver (KSZ9131) wired to a RJ45 plug.
The hardware works fine when connected to a gigabit switch or router however when connected to a 100BASE-TX router the PFE0 TX clock does not get set to 25MHz and remains at 125MHz which is the speed for gigabit.
After some investigating I can see that the pfe0 tx clock comes from these two muxes:
EMAC0 mux
CGM2 Mux 1 with divider. Setting this divider to this value (5) is what we need the kernel (and SCMI I suppose) to be able to do.
The pfeng driver seems to think it is setting the clock to 25MHz
however probing the physical pfe0 tx pin shows the old 125MHz clock and there is no ethernet traffic passing through.
I believe SCMI running in BL31 (part of TF-A) is responsible for clock management.
I have tried patching the CGM2 part of the TF-A device tree to specify the 25MHz clock:
diff --git a/fdts/s32g.dtsi b/fdts/s32g.dtsi
index 14ba9729d..02cd393e4 100644
--- a/fdts/s32g.dtsi
+++ b/fdts/s32g.dtsi
@@ -604,12 +604,15 @@
assigned-clocks =
<&plat_clks S32G_CLK_MC_CGM2_MUX0>,
+ <&plat_clks S32G_CLK_MC_CGM2_MUX1>,
<&plat_clks S32G_CLK_PFE_PE>;
assigned-clock-rates =
<0>,
+ <25000000>,
<600000000>;
assigned-clock-parents =
- <&plat_clks S32G_CLK_ACCEL_PLL_PHI1>;
+ <&plat_clks S32G_CLK_ACCEL_PLL_PHI1>,
+ <&plat_clks S32GEN1_CLK_PERIPH_PLL_PHI5>;
};
pfe: pfe@46000000 {
And also this printout where the mux gets enabled to check when and how it's being set
diff --git a/drivers/nxp/s32/clk/enable_clk.c b/drivers/nxp/s32/clk/enable_clk.c
index a356da96c..24c1e59ec 100644
--- a/drivers/nxp/s32/clk/enable_clk.c
+++ b/drivers/nxp/s32/clk/enable_clk.c
@@ -762,7 +762,10 @@ static int enable_cgm_div(struct s32gen1_clk_obj *module,
return -EINVAL;
#endif
}
-
+ if(cgm_addr == (void*)MC_CGM2_BASE_ADDR){
+ NOTICE("\r\nEnabling CGM2 mux %d with div scaling %d\r\n",mux->index, dc);
+ NOTICE("\r\npfreq %lu div->freq %lu\r\n",pfreq, div->freq);
+ }
cgm_mux_div_config(cgm_addr, mux->index, dc - 1, div->index);
return 0;
}
The shell clearly outputs that the mux is being enabled with the divider set to 5 however this doesn't seem to work.
I have found a temporary workaround of just setting the PHI5 output of the peripheral pll to 25MHz via this patch which does work and enables 100Base tx communications
diff --git a/fdts/s32cc.dtsi b/fdts/s32cc.dtsi
index 15ee06089..d8177c12b 100644
--- a/fdts/s32cc.dtsi
+++ b/fdts/s32cc.dtsi
@@ -428,7 +428,7 @@
<S32GEN1_PERIPH_PLL_VCO_FREQ>, <100000000>,
<80000000>, <80000000>,
<125000000>, <200000000>,
- <125000000>, <100000000>;
+ <25000000>, <100000000>;
};
accelpll: accelpll@40040000 {
This isn't ideal since we might have other things reliant on the PHI5 clock that need a different frequency. The divider of CGM2 Mux 1 seems like an easier thing to modify.
I'm running at-f 2.5 from bsp39 and kernel 5.15 from bsp39 as well but tried 5.10 from bsp38 with no difference
