S32G3 GMAC pps output config in bsp41

[XD]

Hi,

How do I configure the GMAC PPS output pin in the device tree? We are running GMAC in SGMII mode, and I am trying to configure PA_12 (GMAC PPS[3]) as the GMAC PPS output. Should I create a separate PPS entry, or should it be added to the GMAC node in the device tree? Could you provide an example?

Thanks,

XD

[carlos_o]

Hi @XD,

Thanks for your questions.

You can locate the needed information to the configurations at the S32G3_IOMUX.xls file attached to the S32G3 Reference Manual.

As you can see GMAC0_PSS[3] is the option 0000_0001, so at the device tree we need to configure that pin as FUNC1

In this example I will use as reference the S32G RDB3 board.

So, I modify the file s32g399a-rdb3.dts with the following:

&gmac0 {
    pinctrl-names = "default";
    pinctrl-0 = <&gmac_out_pins>;
    status = "okay";
}

&pinctrl {
    gmac0_out_pins: gmac0_out_pins {
        gmac0_out_grp {
            pinmux = <S32CC_PINMUX(12, FUNC1)>;
            output-enable;
        }
    }
}

[XD]

Hi @carlos_o ,

Thank you for your support, Carlos.

In addition to the device tree change, do we need to perform any extra GMAC register configuration? Or will the GMAC driver configure the appropriate registers based on the device tree PPS configuration?

I’m asking because I noticed that GMAC has the MAC_PPS_Control (B70) register. I tried manually rewriting it, but it appears to be protected—any write operation causes a kernel panic.

Thanks,

XD

[carlos_o]

Hi @XD, 

Unfortunately, this is out of my scope of expertise and the internal team is now on a free time. So, you can try your current configuration, if it fails, we can try to figure out a resolution to it. 

Please share the outputs you get and also if you can the PPS device tree configuration you are implementing. 

For a better understanding of your context. Are you using a custom board? if not, is it an RDB or EVB board?

[XD]

Hi @carlos_o ,

After applying the device tree change (pps[3]), it seems that the MAC_PPS_CONTROL register (0xB70) is still not configuring the PPS output. I also attempted to use ethtool to enable the PPS, but it was unsuccessful. Could you please forward this information to the internal team and let me know the necessary steps to enable the PPS output on GMAC0?

Thanks,

XD

root@s32g399ardb3:~# devmem2 0x4033c110 w
/dev/mem opened.
Memory mapped at address 0x7fae22f000.
Read at address  0x4033C110 (0x7fae22f110): 0x00001052
root@s32g399ardb3:~# devmem2 0x4033c124 w                                                                                                                                                                  
/dev/mem opened.
Memory mapped at address 0x7faf1d1000.
Read at address  0x4033C124 (0x7faf1d1124): 0x44104104
root@s32g399ardb3:~# devmem2 0x4033cb70 w                                                                                                                                                                  
/dev/mem opened.
Memory mapped at address 0x7fa3957000.
Read at address  0x4033CB70 (0x7fa3957b70): 0x00000000

[carlos_o]

Hi @XD,

The internal team want to know how you are trying to configure the PPS registers. 

Also, they recommend review the following information:

[Page 811, GMAC Subsystem RM, Rev. 2, 02/2023]

[Page 905, GMAC Subsystem RM, Rev. 2, 02/2023]

[Page 906, GMAC Subsystem RM, Rev. 2, 02/2023] 

[XD]

Hi @carlos_o ,

Thank you for the update.

I attempted to use devmem2 to modify the MAC_PPS_CONTROL register (0xB70), specifically the ppscmd and enable bits. However, this caused a kernel panic. I’ve attached a screenshot for reference.

Could you advise on the correct method for reading and writing GMAC registers?

Thanks,

XD

[carlos_o]

Hi @XD, 

devmem2 is not supported for the registers that has a write protection. If you want to access those registers from user space, you can do the following:

Invoke the kernel menuconfig

If are working with a Yocto build the command is:

$bitbake virtual/kernel -c menuconfig

If you work with the manual build from your linux repository the command is:

$make menuconfig

then go in --> Device Drivers --> SOC (System On Chip) specific Drivers -->NXP Userspace Reg Access Driver

and select:

<*>Userspace accessto soc registers
as below:

 

Rebuild the kernel

If you are using yocto deploy the image.

The you can either reflash the full image or just replace "Image" in the "boot_s32g3" partition of your SD card / eMMC.

With this new image at your userspace you can write on the register as following:

root@s32g399ardb3:~# echo 0x4009C24C 32 0x00123000 > /sys/kernel/s32cc_regaccess/write

this is as 

echo [register_address] {access_width} [register_data] > /sys/kernel/s32cc_regaccess/write

for read register you can also use this without the register_data writting an echo to /sys/kernel/s32cc_regaccess/read

[XD]

Hi @carlos_o ,

Thank you for the detailed instructions; this is exactly what I need.

Unfortunately, the kernel I built using bsp41 Yocto is version 5.15, and there is no 'NXP Userspace Reg Access Driver' under 'SOC (System On Chip) specific Drivers.' I have attached a screenshot. Is there a way to enable it with the 5.15 kernel?

Thanks,

XD 

[carlos_o · Accepted solution]

Hi @XD,

The BSP41 User Manual says that configuration is available, but in my workspace, I was only able to see it at the secondary kernel of BSP41.

[Page 160, Linux BSP 41.0 User Manual for S32G3 platforms]

[Page 2, Linux BSP 41.0 Release Notes for S32G3]

Try to enable it using the secondary kernel of this BSP version (to debug purpose). Then with this you can try the configuration of the PPS register, after that you can develop a kernel driver to write the desire values to the registers. 

[XD]

Hi @carlos_o ,

Thank you for the update, I appreciate it. Maybe I should switch to 6.6.25 to make it easier.

Thanks,

XD

[carlos_o]

Glad to help!

[carlos_o]

Hi @XD, 

Thanks for sharing your output. I'll review with the internal team how to properly configure the PPS with GMAC0. I'll come back ASAP with further information. We appreciate your patience. 

[XD]

Hi @carlos_o ,

Thank you for your quick response.

I will read those registers back after applying the device tree change.

This is on our custom board, and we are using SGMII on GMAC.

Thanks,

XD