S32G3 ASIL Levels

[srinivasboppidi]

1. Can performance cores and Realtime cores be considered ASIL-B independent? Under what conditions?

2. Is redundant software execution required if ASIL-B SW gets executed on decoupled performance cores on S32G3 (SM4.A53.SWCMP AoU) – what other alternatives would be possible?

[leofrenchheheh]

There are four ASILs identified by ISO 26262: A, B, C and D. ASIL A represents the lowest grade and ASIL D represents the highest grade of automotive risk.

Regards: Pixellab mod apk

[Daniel-Aguirre]

Hi,

Below will be some comments on regards of your questions:

Q1 >> Can performance cores and Realtime cores be considered ASIL-B independent? Under what conditions?

A1 >> Can you elaborate more on what "ASIL-B independent" refers to?

For S32G3, under the A53 cores, the following is said [Table 2, Page 6, S32G3 Data Sheet, Rev. 2, 02/2023]:

"Configurable ASIL D lockstep clusters and two ASIL B independent clusters "

As for the M7 cores inside the S32G3 platform, they are already configured as "Dual-core lockstep", this configuration cannot be changed.

Q2 >> Is redundant software execution required if ASIL-B SW gets executed on decoupled performance cores on S32G3 (SM4.A53.SWCMP AoU) – what other alternatives would be possible?

A2 >> This seems to be FuSa requirements rather than platform requirement. We might suggest sending this specific inquiry to your local NXP FAE, for them to channel your questions adequately. The platform itself is ASIL-D (if configured as lockstep clusters) or ASIL-B (if configured as independent clusters) under the A53 cores. For the SW to be ASIL-B compliant, that might be another story not directly related to the HW platform.

Please, let us know.

[srinivasboppidi]

Hi,

Thank You for Your Reply,

Please send this enquiry to FUSA Team since These Queries are related to FUSA only.

for Q1 : they have not mentioned any conditions Here [Table 2, Page 6, S32G3 Data Sheet, Rev. 2, 02/2023] any specific conditions to configure two ASIL B independent ?

[Daniel-Aguirre]

Hi,

Thanks for your feedback.

Since FuSa information related to S32G is under NDA, we assume you are going to send this information to your local NXP FAE, for a more secure channel.

As for Q1, we apologize for our insistence, can you elaborate more on what "two ASIL B independent" means?

Please, let us know.

[srinivasboppidi]

Hi ,

Thanks for your quick Reply,

Yes , I have valid NDA , I already sent once so they added me to this community, could you please send my query to your FUSA team to answer the below question  mean while I get more details of Q1 as you requested.

Q2. Is redundant software execution required if ASIL-B SW gets executed on decoupled performance cores on S32G3 (SM4.A53.SWCMP AoU) – what other alternatives would be possible?

[asap]

hi Srinivasboppidi,

you may follow SafeAssure NDA group to raise your FuSa related questions into that community. 

[srinivasboppidi]

Hi Albert,

I have raised posted these queries in the Safe Assure NDA Group but no response from anyone 

S32G3 FuSA Related Queries - NXP Community

[srinivasboppidi]

Please Help me out in these queries

[asap]

Srinivasboppidi,

as explained, you should go to the FuSa specific community (instead of this S32G product forum) to raise your Functional safety related question, the resource link has been provided to you. And you could reach out your local NXP representatives for more info.

albert

[srinivasboppidi]

Hi,

Thank You for Your Reply,

Please send this enquiry to FUSA Team since These Queries are related to  FUSA only.

for Q1 : they have not mentioned any conditions Here  [Table 2, Page 6, S32G3 Data Sheet, Rev. 2, 02/2023] any specific conditions to configure two ASIL B independent ?