S32G2: TCM Backdoor memory not accessible

[bastian_schick]

Accoring the manual the each TCM has a backdoor address, e.g. TCM-Core0 should be at 0x2010.0000.

But there is no memory at all.

I cannot find info on how to enable the backdoor access?

Maybe anyone has a pointer where to look at.

Related: Standby SRAM (0x2400.0000) is not accessible as well.

Cheers

42Bastian

[bastian_schick]

Thanks for clarification. Such should be noted fat in the manual.

I assume this applies to Standby SRAM as well? Or"shared HSE" RAM?

So only DDRAM or "general" SRAM can be used to exchange data between CM7 cores, right?

[Daniel-Aguirre]

Hi,

Thanks for your feedback. For core-to-core communication, seems to be that it is as you say. You should also be able to use the IPCF package (link to product page: Inter-Platform Communication Framework (IPCF) | NXP Semiconductors) which is a framework for core-to-core communication.

Please, let us know. 

[bastian_schick]

SCIOPTA Core2Core communication uses a slimlined technic as part of the kernel and does not rely on a any 3rd party framework. But I need to know which core can read/write which memory. A pity that in the S32K3 TCM backdoors are readable but in S32G not. (Design fault or wanted?)
Anyway thx for clarification.

[Daniel-Aguirre]

Hi,

On regards of the TCM Backdoor, the following is told:

"M7 cores cannot access any TCM through backdoor ports. Except M7 cores, the other bus masters, e.g. A53 cores, DMA etc., can access the respective TCMs via backdoor ports.

In other words, M7 can only access its own TCM through TCM port bus and cannot access other M7’s TCM. Non-M7 bus masters can access all M7’s TCMs through respective backdoor ports."

Please, let us know.