Register access for SJA1110 Switch

Atkinson · ‎06-11-2025

Hello @PavelL, @chenyin_h

I would like to access the registers for accessing the L2 Table, VLAN Table via Dynamic

Address Name Access Reset Description
8Ch DYN_BE_LKP_
ENTRY0
R/W 0h
(FFFFFFFEh)
90h DYN_BE_LKP_
ENTRY1
R/W 0h
94h DYN_BE_LKP_
ENTRY2
R/W 0h
98h DYN_BE_LKP_
ENTRY3
R/W 0h
9Ch DYN_BE_LKP_
ENTRY4
R/W 0h
A0h DYN_BE_LKP_
ENTRY5
R/W 0h
A4h DYN_BE_LKP_CTRL R/W 0h
(FF800000h)

How to access the register to configure change it ?
How to change the values of the registers during run Time??
Using Programming Interface we can change it Dynamically (as mentioned in Document) is there any external tool need to configure ??

Regards
Atkinson

Atkinson · ‎07-29-2025

Hi @PavelL

The below is the code which create a Dynamic entry for CB_Sequence Generation and Recovery Table can you check whether the entry is in a Correct order if at all any changes in the order of CB_SGIR_ENtry[0],[1],[2],[3],[4] can you provide me the changes of the order because its not mentioned cb_sg_ir.py

And one more thing cb_sg_ir.py file there is not order for creating a entry its like a parsing of data getentry, setentry can you confirm me the order of array which I have created to make a dynamic entry

what are the changes need to be mentioned in below code can you provide me the valid changes that would be more helpful

int WriteCB_SG_IR(uint32_t index) {

int cs = 0;

uint32_t CBSGIR_OFFSET = 142;

uint32_t CBSGIR_CTRL_OFFSET = 147;

const uint32_t SWREG_BASE = 0;

uint32_t CB_SG_IR_ADDRESS = SWREG_BASE + CBSGIR_OFFSET;

uint32_t CB_SG_IR_ADDRESS_CTL = SWREG_BASE + CBSGIR_CTRL_OFFSET;

if (index >= 64) {

return -1;

}

uint32_t RTAGOFFSET_0 = 0;

uint32_t RTAGOFFSET_1 = 0;

uint32_t RTAGOFFSET_2 = 0;

uint32_t RTAGOFFSET_3 = 0;

uint32_t RTAGOFFSET_4 = 0;

uint32_t RTAGOFFSET_5 = 0;

uint32_t RTAGOFFSET_6 = 0;

uint32_t RTAGOFFSET_7 = 0;

uint32_t RTAGOFFSET_8 = 0;

uint32_t RTAGOFFSET_9 = 0;

uint32_t RTAGOFFSET_10 = 0;

uint32_t REPLACE_PORTS = 0;

uint32_t TAG_PORTS = 0x006;

uint32_t SEQ_REC_PORTS = 0;

uint32_t IND_REC_PORTS = 0;

uint32_t IND_REC_TIMEOUT = 0;

uint32_t SEQRECOFFSET = 0;

uint32_t GENSEQNUM = 0x1;

uint32_t SEQGENRST = 0;

uint32_t VALID = 1U;

uint32_t RDWRSET = 1U;

uint32_t TARGETEDTBL = 0;

uint32_t CB_SG_IR_Entry[CB_SGIR_ADDR_RANGE] = {0};

CB_SG_IR_Entry[0] =(((GENSEQNUM & 0x1) << (1 % 32)) +

((SEQRECOFFSET & 0x1F) << (2 % 32)) +

((IND_REC_TIMEOUT & 0xFFFF) << (7 % 32)));

CB_SG_IR_Entry[1] =

((SEQ_REC_PORTS & 0x7FF) << 0) |

((IND_REC_PORTS & 0x7FF) << 11);

CB_SG_IR_Entry[2] =

(((TAG_PORTS & 0x7FF) << (0 % 32)) +

((REPLACE_PORTS & 0x7FF) << (11 % 32)));

CB_SG_IR_Entry[3] =

(((RTAGOFFSET_0 & 0x3F) << (0 % 32)) +

((RTAGOFFSET_1 & 0x3F) << (6 % 32)) +

((RTAGOFFSET_2 & 0x3F) << (12 % 32)) +

((RTAGOFFSET_3 & 0x3F) << (18 % 32)) +

((RTAGOFFSET_4 & 0x3F) << (24 % 32)));

CB_SG_IR_Entry[4] =

(((RTAGOFFSET_5 & 0x3F) << (0 % 32)) +

((RTAGOFFSET_6 & 0x3F) << (6 % 32)) +

((RTAGOFFSET_7 & 0x3F) << (12 % 32)) +

((RTAGOFFSET_8 & 0x3F) << (18 % 32)) +

((RTAGOFFSET_9 & 0x3F) << (24 % 32)) +

((RTAGOFFSET_10 & 0x3F) << (30 % 32)));

uint32_t status = 0;

status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

uint8_t counter = 0;

while ((status & (1 << 31)) != 0){

counter++;

status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

}

for (int i = 0; i < CB_SGIR_ADDR_RANGE; i++) {

Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS + i, CB_SG_IR_Entry[i]);

if (ret != E_OK) {

return -2;

}

uint32_t readBack = 0;

ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS + i, &readBack);

if (ret != E_OK || readBack != CB_SG_IR_Entry[i]) {

return -3;

}

uint32_t CTRL_VALUE = (VALID << 31) |

(RDWRSET << 30) |

(SEQGENRST << 9) |

(TARGETEDTBL << 6) |

(index & 0x3F);

Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS_CTL, CTRL_VALUE);

if (ret != E_OK) {

return -4;

}

do {

ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, &status);

if (ret != E_OK) {

return -5;

}

} while ((status >> 31) & 1U);

return 0; // Success

}

PavelL · ‎07-29-2025

Hello @Atkinson ,

Based on the official layout of the CB Sequence Generation and Recovery Table (Table 1148) and the Python implementation (cb_sg_ir.py), your field mapping inside each word is correct — but the order of the words in the array CB_SG_IR_Entry[] needs to be reversed.

The correct order is:

Word Index	Fields
entry[0]	IND_REC_TIMEOUT, SEQRECOFFSET, GENSEQNUM
entry[1]	SEQ_REC_PORTS, IND_REC_PORTS
entry[2]	TAG_PORTS, REPLACE_PORTS
entry[3]	RTAGOFFSET_0 to RTAGOFFSET_4
entry[4]	RTAGOFFSET_5 to RTAGOFFSET_10

Best regards,

Pavel

Atkinson · ‎07-30-2025

Hi @PavelL

I tried changing the entry order as you mentioned but there is no positive response in creation of CB_Sequence Generation and Recovery Table
so is that any other changes need to be made in the code ?

I am trying to bring Dynamic L2 Lookup entry which is working fine but the CB_Sequence and Generation and Recovery table is not reflecting in a way that i am unable to tag Port 1 & Port 2 and also GENSEQNUM is not turning up

so what could be the other cause of the issue can you double confirm me whether any other changes need to be made or not

int WriteCB_SG_IR(uint32_t index) {

int cs = 0;

uint32_t CBSGIR_OFFSET = 142;

uint32_t CBSGIR_CTRL_OFFSET = 147;

const uint32_t SWREG_BASE = 0;

uint32_t CB_SG_IR_ADDRESS = SWREG_BASE + CBSGIR_OFFSET;

uint32_t CB_SG_IR_ADDRESS_CTL = SWREG_BASE + CBSGIR_CTRL_OFFSET;

if (index >= 64) {

return -1;

}

uint32_t RTAGOFFSET_0 = 0;

uint32_t RTAGOFFSET_1 = 0;

uint32_t RTAGOFFSET_2 = 0;

uint32_t RTAGOFFSET_3 = 0;

uint32_t RTAGOFFSET_4 = 0;

uint32_t RTAGOFFSET_5 = 0;

uint32_t RTAGOFFSET_6 = 0;

uint32_t RTAGOFFSET_7 = 0;

uint32_t RTAGOFFSET_8 = 0;

uint32_t RTAGOFFSET_9 = 0;

uint32_t RTAGOFFSET_10 = 0;

uint32_t REPLACE_PORTS = 0;

uint32_t TAG_PORTS = 0x006;

uint32_t SEQ_REC_PORTS = 0;

uint32_t IND_REC_PORTS = 0;

uint32_t IND_REC_TIMEOUT = 0;

uint32_t SEQRECOFFSET = 0;

uint32_t GENSEQNUM = 0x1;

uint32_t SEQGENRST = 0;

uint32_t VALID = 1U;

uint32_t RDWRSET = 1U;

uint32_t TARGETEDTBL = 0;

uint32_t CB_SG_IR_Entry[CB_SGIR_ADDR_RANGE] = {0};

CB_SG_IR_Entry[0] = (((IND_REC_TIMEOUT & 0xFFFF) << (1 % 32)) +

((SEQRECOFFSET & 0x1F) << (17 % 32)) +

((GENSEQNUM & 0x1) << (22 % 32)));

CB_SG_IR_Entry[1] =

((SEQ_REC_PORTS & 0x7FF) << 0) |

((IND_REC_PORTS & 0x7FF) << 11);

CB_SG_IR_Entry[2] =

(((TAG_PORTS & 0x7FF) << (0 % 32)) +

((REPLACE_PORTS & 0x7FF) << (11 % 32)));

CB_SG_IR_Entry[3] =

(((RTAGOFFSET_0 & 0x3F) << (0 % 32)) +

((RTAGOFFSET_1 & 0x3F) << (6 % 32)) +

((RTAGOFFSET_2 & 0x3F) << (12 % 32)) +

((RTAGOFFSET_3 & 0x3F) << (18 % 32)) +

((RTAGOFFSET_4 & 0x3F) << (24 % 32)));

CB_SG_IR_Entry[4] =

(((RTAGOFFSET_5 & 0x3F) << (0 % 32)) +

((RTAGOFFSET_6 & 0x3F) << (6 % 32)) +

((RTAGOFFSET_7 & 0x3F) << (12 % 32)) +

((RTAGOFFSET_8 & 0x3F) << (18 % 32)) +

((RTAGOFFSET_9 & 0x3F) << (24 % 32)) +

((RTAGOFFSET_10 & 0x3F) << (30 % 32)));

uint32_t status = 0;

status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

uint8_t counter = 0;

while ((status & (1 << 31)) != 0){

counter++;

status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

}

for (int i = 0; i < CB_SGIR_ADDR_RANGE; i++) {

Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS + i, CB_SG_IR_Entry[i]);

if (ret != E_OK) {

return -2;

}

uint32_t readBack = 0;

ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS + i, &readBack);

if (ret != E_OK || readBack != CB_SG_IR_Entry[i]) {

return -3;

}

uint32_t CTRL_VALUE = (VALID << 31) |

(RDWRSET << 30) |

(SEQGENRST << 9) |

(TARGETEDTBL << 6) |

(index & 0x3F);

Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS_CTL, CTRL_VALUE);

if (ret != E_OK) {

return -4;

}

do {

ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, &status);

if (ret != E_OK) {

return -5;

}

} while ((status >> 31) & 1U);

return 0; // Success

}

PavelL · ‎07-31-2025

Hello @Atkinson ,

I reviewed your latest code, and the structure and word order of the CB_SG_IR_Entry[] array is now correct. However, I noticed a critical issue in the bit shifts used in CB_SG_IR_Entry[0].

According to the hardware specification (Table 1148), the bit positions are:

GENSEQNUM: bit 28
SEQRECOFFSET: bits 29–33
IND_REC_TIMEOUT: bits 34–49

In your current code, these fields are shifted too low. Please update the line as follows:

CB_SG_IR_Entry[0] =

((GENSEQNUM & 0x1) << 28) |

((SEQRECOFFSET & 0x1F) << 29) |

((IND_REC_TIMEOUT & 0xFFFF) << 34);

This should ensure that the GENSEQNUM bit is correctly set and interpreted by the switch.

Also, please double-check that:

REPLACE_PORTS is not overriding TAG_PORTS for ports 1 and 2
The ports are enabled and not filtered by other tables (e.g., ingress/egress filtering)

Best regards,

Pavel

Atkinson · ‎08-01-2025

Hi @PavelL

int WriteCB_SG_IR(uint32_t index) {

int cs = 0;

uint32_t CBSGIR_OFFSET = 142;

uint32_t CBSGIR_CTRL_OFFSET = 147;

const uint32_t SWREG_BASE = 0;

uint32_t CB_SG_IR_ADDRESS = SWREG_BASE + CBSGIR_OFFSET;

uint32_t CB_SG_IR_ADDRESS_CTL = SWREG_BASE + CBSGIR_CTRL_OFFSET;

if (index >= 64) {

return -1;

}

uint32_t RTAGOFFSET_0 = 0;

uint32_t RTAGOFFSET_1 = 0;

uint32_t RTAGOFFSET_2 = 0;

uint32_t RTAGOFFSET_3 = 0;

uint32_t RTAGOFFSET_4 = 0;

uint32_t RTAGOFFSET_5 = 0;

uint32_t RTAGOFFSET_6 = 0;

uint32_t RTAGOFFSET_7 = 0;

uint32_t RTAGOFFSET_8 = 0;

uint32_t RTAGOFFSET_9 = 0;

uint32_t RTAGOFFSET_10 = 0;

uint32_t REPLACE_PORTS = 0;

uint32_t TAG_PORTS = 0x7FF;

uint32_t SEQ_REC_PORTS = 0;

uint32_t IND_REC_PORTS = 0;

uint32_t IND_REC_TIMEOUT = 0;

uint32_t SEQRECOFFSET = 0;

uint32_t GENSEQNUM = 0x1;

uint32_t SEQGENRST = 0;

uint32_t VALID = 1U;

uint32_t RDWRSET = 1U;

uint32_t TARGETEDTBL = 0;

uint64_t CB_SG_IR_Entry[CB_SGIR_ADDR_RANGE] = {0};

CB_SG_IR_Entry[0] =

((GENSEQNUM & 0x1) << 28) |

((SEQRECOFFSET & 0x1F) << 29) |

((IND_REC_TIMEOUT & 0xFFFF) << 34);

CB_SG_IR_Entry[1] =

((SEQ_REC_PORTS & 0x7FF) << 0) |

((IND_REC_PORTS & 0x7FF) << 11);

CB_SG_IR_Entry[2] =

((TAG_PORTS & 0x7FF) << 0) |

((REPLACE_PORTS & 0x7FF) << 11);

CB_SG_IR_Entry[3] =

((RTAGOFFSET_0 & 0x3F) << 0) |

((RTAGOFFSET_1 & 0x3F) << 6) |

((RTAGOFFSET_2 & 0x3F) << 12) |

((RTAGOFFSET_3 & 0x3F) << 18) |

((RTAGOFFSET_4 & 0x3F) << 24);

CB_SG_IR_Entry[4] =

((RTAGOFFSET_5 & 0x3F) << 0) |

((RTAGOFFSET_6 & 0x3F) << 6) |

((RTAGOFFSET_7 & 0x3F) << 12) |

((RTAGOFFSET_8 & 0x3F) << 18) |

((RTAGOFFSET_9 & 0x3F) << 24) |

((RTAGOFFSET_10 & 0x3F) << 30);

uint32_t status = 0;

status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

uint8_t counter = 0;

while ((status & (1 << 31)) != 0){

counter++;

status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

}

for (int i = 0; i < CB_SGIR_ADDR_RANGE; i++) {

Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS + i, CB_SG_IR_Entry[i]);

if (ret != E_OK) {

return -2;

}

uint32_t readBack = 0;

ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS + i, &readBack);

if (ret != E_OK || readBack != CB_SG_IR_Entry[i]) {

return -3;

}

uint32_t CTRL_VALUE = (VALID << 31) |

(RDWRSET << 30) |

(SEQGENRST << 9) |

(TARGETEDTBL << 6) |

(index & 0x3F);

Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS_CTL, CTRL_VALUE);

if (ret != E_OK) {

return -4;

}

do {

ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, &status);

if (ret != E_OK) {

return -5;

}

} while ((status >> 31) & 1U);

return 0; // Success

}

I have modified the code respective to advise
Still i am facing the issue with creation of Dynamic Entry in CB Sequence Generation and Recovery Table can you double check once which might be helpful
and one more thing whether we need to create 5 entry with 64 bit in size or 5 entry with 32 bit in size
i am thinking the issue might be root cause of entry creation
IND_REC_TIMEOUT is getting overwhelmed with 34

so can i provide me the complete entry 0 to 4 which will be creating a Dynamic Entry

PavelL · ‎08-04-2025

Hello @Atkinson ,

Thank you for the updated code. I reviewed your implementation and the field mapping and bit shifts are now correct. However, I noticed a critical issue that may be the root cause:

You are currently using:

uint64_t CB_SG_IR_Entry[5];

But according to the hardware specification and the reference Python implementation, each entry word should be 32 bits, not 64 bits. The switch expects 5 × 32-bit words for each CB_SG_IR entry.

Please change this to:

uint32_t CB_SG_IR_Entry[5];

Using 64-bit values may cause incorrect register writes or misalignment in SPI communication. Also, make sure that your spi_write_DynamicEntry() and spi_read_DynamicEntry() functions operate on 32-bit values.

Additionally, when validating the write-back values, ensure that the comparison is done correctly:

uint32_t readBack = 0;

ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS + i, &readBack);

if (ret != E_OK || readBack != CB_SG_IR_Entry[i]) {

return -3;

}

Best regards,

Pavel

Atkinson · ‎08-05-2025

Hi @PavelL

int WriteCB_SG_IR(uint32_t index) {

int cs = 0;

uint32_t CBSGIR_OFFSET = 142;

uint32_t CBSGIR_CTRL_OFFSET = 147;

const uint32_t SWREG_BASE = 0;

uint32_t CB_SG_IR_ADDRESS = SWREG_BASE + CBSGIR_OFFSET;

uint32_t CB_SG_IR_ADDRESS_CTL = SWREG_BASE + CBSGIR_CTRL_OFFSET;

if (index >= 64) {

return -1;

}

uint32_t RTAGOFFSET_0 = 0;

uint32_t RTAGOFFSET_1 = 0;

uint32_t RTAGOFFSET_2 = 0;

uint32_t RTAGOFFSET_3 = 0;

uint32_t RTAGOFFSET_4 = 0;

uint32_t RTAGOFFSET_5 = 0;

uint32_t RTAGOFFSET_6 = 0;

uint32_t RTAGOFFSET_7 = 0;

uint32_t RTAGOFFSET_8 = 0;

uint32_t RTAGOFFSET_9 = 0;

uint32_t RTAGOFFSET_10 = 0;

uint32_t REPLACE_PORTS = 0;

uint32_t TAG_PORTS = 0x7FF;

uint32_t SEQ_REC_PORTS = 0;

uint32_t IND_REC_PORTS = 0;

uint32_t IND_REC_TIMEOUT = 0;

uint32_t SEQRECOFFSET = 0;

uint32_t GENSEQNUM = 0x1;

uint32_t SEQGENRST = 0;

uint32_t VALID = 1U;

uint32_t RDWRSET = 1U;

uint32_t TARGETEDTBL = 0;

uint32_t CB_SG_IR_Entry[CB_SGIR_ADDR_RANGE] = {0};

CB_SG_IR_Entry[0] =

((GENSEQNUM & 0x1) << 28) |

((SEQRECOFFSET & 0x1F) << 29) |

((IND_REC_TIMEOUT & 0xFFFF) << 34);

CB_SG_IR_Entry[1] =

((SEQ_REC_PORTS & 0x7FF) << 0) |

((IND_REC_PORTS & 0x7FF) << 11);

CB_SG_IR_Entry[2] =

((TAG_PORTS & 0x7FF) << 0) |

((REPLACE_PORTS & 0x7FF) << 11);

CB_SG_IR_Entry[3] =

((RTAGOFFSET_0 & 0x3F) << 0) |

((RTAGOFFSET_1 & 0x3F) << 6) |

((RTAGOFFSET_2 & 0x3F) << 12) |

((RTAGOFFSET_3 & 0x3F) << 18) |

((RTAGOFFSET_4 & 0x3F) << 24);

CB_SG_IR_Entry[4] =

((RTAGOFFSET_5 & 0x3F) << 0) |

((RTAGOFFSET_6 & 0x3F) << 6) |

((RTAGOFFSET_7 & 0x3F) << 12) |

((RTAGOFFSET_8 & 0x3F) << 18) |

((RTAGOFFSET_9 & 0x3F) << 24) |

((RTAGOFFSET_10 & 0x3F) << 30);

uint32_t status = 0;

status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

uint8_t counter = 0;

while ((status & (1 << 31)) != 0){

counter++;

status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

}

for (int i = 0; i < CB_SGIR_ADDR_RANGE; i++) {

Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS + i, CB_SG_IR_Entry[i]);

if (ret != E_OK) {

return -2;

}

uint32_t readBack = 0;

ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS + i, &readBack);

if (ret != E_OK || readBack != CB_SG_IR_Entry[i]) {

return -3;

}

uint32_t CTRL_VALUE = (VALID << 31) |

(RDWRSET << 30) |

(SEQGENRST << 9) |

(TARGETEDTBL << 6) |

(index & 0x3F);

Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS_CTL, CTRL_VALUE);

if (ret != E_OK) {

return -4;

}

do {

ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, &status);

if (ret != E_OK) {

return -5;

}

} while ((status >> 31) & 1U);

return 0; // Success

}

So i changed the configuration as you mentioned but still its not able to create a Dynamic Entry.
Add on to that, see when we are configuring this
((GENSEQNUM & 0x1) << 28) |
((SEQRECOFFSET & 0x1F) << 29) |
((IND_REC_TIMEOUT & 0xFFFF) << 34);

IND_REC_TIMEOUT value is written after 32 bit register value which is we are exceeding the 32 bits where the values will be written into the wrong register ryt?? can you double check whether it will be written within 32bit register

One more thing when i debug, i could see the CB_SG_IR_Entry[0] is written with some values what we are expecting to write but in the case of other CB_SG_IR_Entr[1],[2],[3] there is no value written
I am thinking the root cause of the issue is due to bit change ??

As you mentioned the spi_read and spi_write is as same as L2 Lookup table which i used to configure dynamically which is working fine in L2 Lookup table.
Is there any other thing we are missing out ??

PavelL · ‎08-14-2025

Hello @Atkinson ,

I apologize for the delayed response — I was on vacation.

Thank you for creating a new query, so this thread will continue there:

How to create a Dynamic Entry for CB_SG_IR in S32G-VNP-RDB - NXP Community

I will do my best to answer within this week.

Best regards,

Pavel