How to create a Dynamic Entry for CB_SG_IR in S32G-VNP-RDB

[Atkinson]

int WriteCB_SG_IR(uint32_t index) {

int cs = 0;

uint32_t CBSGIR_OFFSET     = 142;

uint32_t CBSGIR_CTRL_OFFSET = 147;

const uint32_t SWREG_BASE    = 0;

uint32_t CB_SG_IR_ADDRESS      = SWREG_BASE + CBSGIR_OFFSET;

uint32_t CB_SG_IR_ADDRESS_CTL  = SWREG_BASE + CBSGIR_CTRL_OFFSET;

if (index >= 64) {

        return -1;

    }

    uint32_t RTAGOFFSET_0 = 0;

    uint32_t RTAGOFFSET_1 = 0;

    uint32_t RTAGOFFSET_2 = 0;

    uint32_t RTAGOFFSET_3 = 0;

    uint32_t RTAGOFFSET_4 = 0;

    uint32_t RTAGOFFSET_5 = 0;

    uint32_t RTAGOFFSET_6 = 0;

    uint32_t RTAGOFFSET_7 = 0;

    uint32_t RTAGOFFSET_8 = 0;

    uint32_t RTAGOFFSET_9 = 0;

    uint32_t RTAGOFFSET_10 = 0;

    uint32_t REPLACE_PORTS = 0;

    uint32_t TAG_PORTS = 0x7FF;

    uint32_t SEQ_REC_PORTS = 0;

    uint32_t IND_REC_PORTS = 0;

    uint32_t IND_REC_TIMEOUT = 0;

    uint32_t SEQRECOFFSET = 0;

    uint32_t GENSEQNUM = 0x1;

    uint32_t SEQGENRST = 0;

    uint32_t VALID = 1U;

    uint32_t RDWRSET = 1U;

    uint32_t TARGETEDTBL = 0;

    uint32_t CB_SG_IR_Entry[CB_SGIR_ADDR_RANGE] = {0};

    CB_SG_IR_Entry[0] =

    ((GENSEQNUM & 0x1) << 28) |

    ((SEQRECOFFSET & 0x1F) << 29) |

    ((IND_REC_TIMEOUT & 0xFFFF) << 34);

    CB_SG_IR_Entry[1] =

    ((SEQ_REC_PORTS & 0x7FF) << 0) |

        ((IND_REC_PORTS & 0x7FF) << 11);

    CB_SG_IR_Entry[2] =

        ((TAG_PORTS & 0x7FF) << 0) |

        ((REPLACE_PORTS & 0x7FF) << 11);

    CB_SG_IR_Entry[3] =

        ((RTAGOFFSET_0 & 0x3F) << 0)  |

        ((RTAGOFFSET_1 & 0x3F) << 6) |

        ((RTAGOFFSET_2 & 0x3F) << 12) |

        ((RTAGOFFSET_3 & 0x3F) << 18) |

        ((RTAGOFFSET_4 & 0x3F) << 24);

    CB_SG_IR_Entry[4] =

        ((RTAGOFFSET_5 & 0x3F) << 0) |

        ((RTAGOFFSET_6 & 0x3F) << 6) |

        ((RTAGOFFSET_7 & 0x3F) << 12) |

        ((RTAGOFFSET_8 & 0x3F) << 18) |

        ((RTAGOFFSET_9 & 0x3F) << 24) |

        ((RTAGOFFSET_10 & 0x3F) << 30);

    uint32_t status = 0;

    status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

    uint8_t counter = 0;

    while ((status & (1 << 31)) != 0){

       counter++;

       status = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, cs);

    }

    for (int i = 0; i < CB_SGIR_ADDR_RANGE; i++) {

    Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS + i, CB_SG_IR_Entry[i]);

    if (ret != E_OK) {

    return -2;

    }

    uint32_t readBack = 0;

    ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS + i, &readBack);

    if (ret != E_OK || readBack != CB_SG_IR_Entry[i]) {

    return -3;

    }

    }

    uint32_t CTRL_VALUE = (VALID << 31) |

                          (RDWRSET << 30) |

                          (SEQGENRST << 9) |

                          (TARGETEDTBL << 6) |

                          (index & 0x3F);

    Std_ReturnType ret = spi_write_DynamicEntry(CB_SG_IR_ADDRESS_CTL, CTRL_VALUE);

        if (ret != E_OK) {

            return -4;

        }

        do {

            ret = spi_read_DynamicEntry(CB_SG_IR_ADDRESS_CTL, &status);

            if (ret != E_OK) {

                return -5;

            }

        } while ((status >> 31) & 1U);

    return 0;  // Success

}

I am trying to create a Dynamic Entry for CB Sequence Generation and Recovery Table in which followed up the example from SJA1110 EVM Host tools CB_SG_IR.py. where i am facing some issue with the bit settings
Add on to that, see when we are configuring this 
((GENSEQNUM & 0x1) << 28) |
((SEQRECOFFSET & 0x1F) << 29) |
((IND_REC_TIMEOUT & 0xFFFF) << 34);

IND_REC_TIMEOUT value is written after 32 bit register value which is we are exceeding the 32 bits where the values will be written into the wrong register ryt?? can you double check whether it will be written within 32bit register 

One more thing when i debug, i could see the CB_SG_IR_Entry[0] is written with some values what we are expecting to write but in the case of other CB_SG_IR_Entr[1],[2],[3] there is no value written 
I am thinking the root cause of the issue is due to bit change ??

As you mentioned the spi_read and spi_write is as same as L2 Lookup table which i used to configure dynamically which is working fine in L2 Lookup table. 
Is there any other thing we are missing out ??

[PavelL]

Hello @Atkinson ,

Finally, I understand your issue clearly.
It turns out the root cause is related to bit alignment across 32-bit words — something quite fundamental when working with hardware register programming. 

Below is the corrected code. I hope I’ve implemented it without errors, but please let me know if anything still looks off.

// Entry[0] – bits 0–31
CB_SG_IR_Entry[0] =
((GENSEQNUM & 0x1) << 28) | // Bit 28
((SEQRECOFFSET & 0x7) << 29); // Bits 29–31

// Entry[1] – bits 32–63
CB_SG_IR_Entry[1] =
((SEQRECOFFSET >> 3) & 0x3) << 0 | // Bits 32–33
((IND_REC_TIMEOUT & 0xFFFF) << 2) | // Bits 34–49
((SEQ_REC_PORTS & 0x7FF) << 18) | // Bits 50–60
((IND_REC_PORTS & 0x7FF) << 29); // Bits 61–71

// Entry[2] – bits 64–95
CB_SG_IR_Entry[2] =
((TAG_PORTS & 0x7FF) << 0) | // Bits 72–82
((REPLACE_PORTS & 0x7FF) << 11) | // Bits 83–93
((RTAGOFFSET_0 & 0x3) << 30); // Bits 94–95 (lower 2 bits)

// Entry[3] – bits 96–127
CB_SG_IR_Entry[3] =
((RTAGOFFSET_0 >> 2) & 0xF) << 0 | // Bits 96–99 (upper 4 bits)
((RTAGOFFSET_1 & 0x3F) << 4) | // Bits 100–105
((RTAGOFFSET_2 & 0x3F) << 10) | // Bits 106–111
((RTAGOFFSET_3 & 0x3F) << 16) | // Bits 112–117
((RTAGOFFSET_4 & 0x3F) << 22) | // Bits 118–123
((RTAGOFFSET_5 & 0xF) << 28); // Bits 124–127 (lower 4 bits)

// Entry[4] – bits 128–159
CB_SG_IR_Entry[4] =
((RTAGOFFSET_5 >> 4) & 0x3) << 0 | // Bits 128–129 (upper 2 bits)
((RTAGOFFSET_6 & 0x3F) << 2) | // Bits 130–135
((RTAGOFFSET_7 & 0x3F) << | // Bits 136–141
((RTAGOFFSET_8 & 0x3F) << 14) | // Bits 142–147
((RTAGOFFSET_9 & 0x3F) << 20) | // Bits 148–153
((RTAGOFFSET_10 & 0x3F) << 26); // Bits 154–159

Best regards,

Pavel

[PavelL]

Hello @Atkinson ,

I adapted example_vlan_lookup_table.py to work with the CB SG IR table. Please find the Python script attached. I’ve also included two .hex files for the SJA1110-EVM, which contain the switchcore configuration for my minimal IEEE 802.1CB example. Just remove the .txt extension from the filenames.

Save all files to the folder where host tools were unzipped, e.g. sja1110evm_hosttools_v1.2\SJA1110EVM

To load the configuration onto the board, follow the DIP switch settings as described in UM575112-AH1901 SJA1110 - EVM User Manual (v1.2), section 3.3 “Quick Start using the Python Host Tools Package”, and run:

python setup_sja1110evm.py --hex1 switchcore_0_Config_CB.hex --hex2 switchcore_1_Config_CB.hex

Then, run the dynamic change example:

python __example_cb_sgir_table.py

You should see output similar to:

CB SG/IR Lookup Table SW0:
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
| IDX | REPLACE_PORTS | TAG_PORTS | IND_REC_PORTS | SEQ_REC_PORTS | IND_REC_TIMEOUT | SEQRECOFFSET | GENSEQNUM |
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
|  0  |       0       |    1056   |       0       |       0       |        0        |      0       |     1     |
|  1  |       0       |     0     |       2       |       2       |        0        |      0       |     0     |
|  2  |       0       |     0     |       2       |       2       |        0        |      0       |     0     |
|  3  |       0       |     0     |       0       |       0       |        0        |      0       |     0     |
...
|  15 |       0       |     0     |       0       |       0       |        0        |      0       |     0     |
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
CB SG/IR Lookup Table SW1:
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
| IDX | REPLACE_PORTS | TAG_PORTS | IND_REC_PORTS | SEQ_REC_PORTS | IND_REC_TIMEOUT | SEQRECOFFSET | GENSEQNUM |
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
|  0  |       0       |     0     |       4       |       4       |        0        |      0       |     0     |
|  1  |       0       |     0     |       4       |       4       |        0        |      0       |     0     |
|  2  |       0       |    1056   |       0       |       0       |        0        |      0       |     1     |
|  3  |       0       |     0     |       0       |       0       |        0        |      0       |     0     |
...
|  15 |       0       |     0     |       0       |       0       |        0        |      0       |     0     |
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
Change entry #1.
[0, 2097152, 1, 0, 0, 0]
Reading again...
CB SG/IR Lookup Table SW0:
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
| IDX | REPLACE_PORTS | TAG_PORTS | IND_REC_PORTS | SEQ_REC_PORTS | IND_REC_TIMEOUT | SEQRECOFFSET | GENSEQNUM |
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
|  0  |       0       |    1056   |       0       |       0       |        0        |      0       |     1     |
|  1  |       0       |     0     |       8       |       8       |        0        |      0       |     0     |
|  2  |       0       |     0     |       2       |       2       |        0        |      0       |     0     |
|  3  |       0       |     0     |       0       |       0       |        0        |      0       |     0     |
...
|  15 |       0       |     0     |       0       |       0       |        0        |      0       |     0     |
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
CB SG/IR Lookup Table SW1:
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
| IDX | REPLACE_PORTS | TAG_PORTS | IND_REC_PORTS | SEQ_REC_PORTS | IND_REC_TIMEOUT | SEQRECOFFSET | GENSEQNUM |
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+
|  0  |       0       |     0     |       4       |       4       |        0        |      0       |     0     |
|  1  |       0       |     0     |       4       |       4       |        0        |      0       |     0     |
|  2  |       0       |    1056   |       0       |       0       |        0        |      0       |     1     |
|  3  |       0       |     0     |       0       |       0       |        0        |      0       |     0     |
...
|  15 |       0       |     0     |       0       |       0       |        0        |      0       |     0     |
+-----+---------------+-----------+---------------+---------------+-----------------+--------------+-----------+

Best regards,

Pavel