Register access for SJA1110 Switch

[Atkinson]

Hello @PavelL, @chenyin_h 

I would like to access the registers for accessing the L2 Table, VLAN Table via Dynamic 

Address Name Access Reset Description
8Ch DYN_BE_LKP_
ENTRY0
R/W 0h
(FFFFFFFEh)
90h DYN_BE_LKP_
ENTRY1
R/W 0h
94h DYN_BE_LKP_
ENTRY2
R/W 0h
98h DYN_BE_LKP_
ENTRY3
R/W 0h
9Ch DYN_BE_LKP_
ENTRY4
R/W 0h
A0h DYN_BE_LKP_
ENTRY5
R/W 0h
A4h DYN_BE_LKP_CTRL R/W 0h
(FF800000h)

How to access the register to configure change it ?
How to change the values of the registers during run Time??
Using Programming Interface we can change it Dynamically (as mentioned in Document) is there any external tool need to configure ??

Regards 
Atkinson 

[PavelL]

Hello @Atkinson ,

Please kindly review:

• AN12925 - chapter 5.1.3 Example for dynamic configuration
• source code of ECT server - src/dynamic_switch_configuration.c - e.g. SJA1110_SetL2LookupTableEntry
• sja1110evm_hosttools_v1.2\SJA1110EVM\write_l2_lookup_table.py

Best regards,

Pavel

[Atkinson]

what is the full form of ECT
Is there any other method of Accessing the Registers for Reading and writing the Values in Register instead of ECT

Regards
Atkinson

[PavelL]

Hello @Atkinson ,

ECT means Ethernet Configuration Tool. It allows you to configure SJA1110 on-line, without flashing.

The other way to access registers in SJA1110 is via SPI. Since register access might not always be straightforward, you may also refer to the supporting Python script for the SJA1110-EVM. It provides a clear view of how to access various registers via SPI.
The Python tools are available on the SJA1110-EVM main page SJA1110-EVM Evaluation Board | NXP Semiconductors  , under Software, Secure files.

Best regards,

Pavel

[Atkinson]

Hello @PavelL 
can you provide me more details about How to access the Registers via SPI 
How to do change the Values via SPI through any external Device we need to change the Values

Regards
Atkinson 

[PavelL]

Hello @Atkinson ,

The fastest way forward is to take inspiration from the SJA1110-EVM — both the hardware (schematics) and the software (Python tools from sja1110evm_hosttools). This can serve as a solid reference point to accelerate your development.

Best regards,

Pavel

[Atkinson]

Hello @PavelL 

I would like to understand,
When we configure the L2 Lookup Table with the respective configuration like MAC, SRCPORT, DSTPORT, CB_ON_DEST, CB_SID_IN so when we configure this configuration statically and Update code 
how these configurations are internally configured in the code & where it is configured 
When we configure like this where these configurations are getting loaded so example: whether this thing is stored as a Binary when the system boots the Binary file with the configuration getting loaded or in a different way 
How this configured file is used into the code 
can you give me some brief explanation 
How this static and Dynamic configuration in run-time works?

Regards
Atkinson

[PavelL]

Hello @Atkinson ,

I believe AN12925, particularly chapter 5.1 "Static and dynamic switch configuration", provides a good overview of how static and dynamic configurations are handled in the SJA1110 system.

To clarify briefly:

- The system always boots with a static configuration, which is compiled into the firmware image.

- During initialization, this configuration is loaded into internal memory, where it is processed and used to configure the switch.

- If dynamic configuration is used, it operates on top of this static setup - typically via host tools or scripts - and is also stored in internal memory.

Details such as how the configuration is internally processed, how long it takes, or how the IP handles it are part of the internal implementation and not publicly documented.

Best regards,

Pavel

[Atkinson]

Hello @PavelL 

In order to understand deep dive into the static configuration 
can you provide me how the flow chart of the static configuration will be there 

whether static and dynamic configuration utilize the same register for storing the data ??
in Static configuration after generating the code in which file i can see the code ??
so whether you are saying when the system boots the generated configuration of tables will be loaded as a binary which will be used ?? am i right ?

Regards
Atkinson 

[PavelL]

Hello @Atkinson 

Let me address your questions point by point:

1. "Can you provide a flow chart of the static configuration?"

If this is not covered in AN12925 or UM11107, then unfortunately it is not public information. The internal flow is part of the implementation and cannot be shared.

2. "Do static and dynamic configurations use the same registers?"

This is a reasonable assumption from a user-level perspective. However, the term "register" is a simplification — the actual implementation is more complex and handled by internal IP blocks.

3. "Where can I find the generated code for static configuration?"

If you're using S32 Design Studio with the SJA1110 SDK, the output files are typically:

•  Debug_FLASH\flash_image.bin — contains both the switch core configuration and the internal MCU code.
•  board\switchcore_0_Config.hex — contains the switch core configuration in the Generic Loader format, as described in Figure 102 of UM11107 rev. 2.0.

 4. "Is the configuration loaded as a binary at boot?"

Yes, that's correct. The configuration is compiled into a binary and loaded during system boot.

Best regards,

Pavel

[Atkinson]

Hello @PavelL 

I would like to configure L2 lookup Table dynamically 
How can i configure the L2 Lookup Table without ECT Tool ? is L2 Lookup table can be configure via Dynamically with ECT Tool How to perform this?
can you give me example ?

Regards
Atkinson

[PavelL]

Hello @Atkinson ,

Let me summarize what we’ve already discussed in this thread and outline the available options for dynamically reconfiguring the L2 Lookup Table on the SJA1110 switch:

1. ECT (Ethernet Control Tool)
Dynamic configuration via external Ethernet (UDP) frames. The internal firmware running on the M7 core receives the configuration and applies it to the switch core.

2. Modified ECT
The ECT source code can be adapted to accept any Ethernet frame format (not just UDP). This allows integration into custom protocols or systems. The internal logic remains the same — the M7 core performs the actual register updates.

3. SPI_HAP (Host Access Protocol)
The write_l2_lookup_table.py script from the host tools demonstrates how to configure the L2 table dynamically via SPI. This approach can be used by any external MCU or host processor. The logic from this script can also be ported to run directly on the internal M7 core if needed.

All of the above methods follow the same principle described in AN12925, section 5.1.3.2. The register-level flow is identical and includes polling the control register, writing to the entry registers, and triggering the update via the control register.

Best regards,

Pavel

[Atkinson]

Hi @PavelL 

Whether it is possible to configure the CB Sequence Generation and Recovery Table and CB Recovery Table can be configured Dynamically whether we have Provision for that ?

By using SJA1110 EVM Host tools whether we have support for that or it is not possible to configure it Dynamically only it can be statically configured in Switchcore?

[PavelL]

Hello @Atkinson ,

The CB Sequence Generation and Recovery Table and CB Recovery Table can be dynamically reconfigured, as described in UM11107, Chapter 5.6.5 – Redundancy Reconfiguration.

This functionality is supported by the SJA1110 EVM Host Tools. Relevant implementation details can be found in the following Python modules:

• cb_sg_ir.py
• cb_sr.py

These are located under the path:
sja1110evm_hosttools_v1.2\SJA1110EVM\SJA1110\

Please note that while the capability is implemented, no directly executable example is provided within the toolset.

Best regards,

Pavel

[Atkinson]

Hi @PavelL 

Can you provide me a Example for Creating a Dynamic Enrty in CB_SG_IR Table 

self.RTAGOFFSET_10 = 0

        self.RTAGOFFSET_9 = 0

        self.RTAGOFFSET_8 = 0

        self.RTAGOFFSET_7 = 0

        self.RTAGOFFSET_6 = 0

        self.RTAGOFFSET_5 = 0

        self.RTAGOFFSET_4 = 0

        self.RTAGOFFSET_3 = 0

        self.RTAGOFFSET_2 = 0

        self.RTAGOFFSET_1 = 0

        self.RTAGOFFSET_0 = 0

        self.REPLACE_PORTS = 0

        self.TAG_PORTS = 0

        self.IND_REC_PORTS = 0

        self.SEQ_REC_PORTS = 0

        self.IND_REC_TIMEOUT = 0

        self.SEQRECOFFSET = 0

        self.GENSEQNUM = 0

        self.tstled = 0

        self.rstled = 0

        self.seqgenrst = 0
How i should mention in this example 
TAG_PORTS =Port 1 & Port 2 
GENSEQNUM = ENABLE 
SEQ_REC_PORTS = POrt 3 & Port 4 

how to enter the values in this data ??

typedef struct {

    uint8_t  RTAGOFFSET_10;

    uint8_t  RTAGOFFSET_9;

    uint8_t  RTAGOFFSET_8;

    uint8_t  RTAGOFFSET_7;

    uint8_t  RTAGOFFSET_6;

    uint8_t  RTAGOFFSET_5;

    uint8_t  RTAGOFFSET_4;

    uint8_t  RTAGOFFSET_3;

    uint8_t  RTAGOFFSET_2;

    uint8_t  RTAGOFFSET_1;

    uint8_t  RTAGOFFSET_0;

    uint16_t REPLACE_PORTS;

    uint16_t TAG_PORTS;

    uint16_t IND_REC_PORTS;

    uint16_t SEQ_REC_PORTS;

    uint16_t IND_REC_TIMEOUT;

    uint16_t SEQRECOFFSET;

    uint16_t GENSEQNUM;

    uint8_t tstled;

    uint8_t rstled;

    uint8_t seqgenrst;

    uint8_t index;

} CB_SGIR_Entry;

void SGIR_Entry(const CB_SGIR_Entry* entry, uint32_t* Write_SGIR_Entry) {

    int ADDR_RANGE = 5;

    for (int i = 0; i < ADDR_RANGE; i++) Write_SGIR_Entry[i] = 0;

    Write_SGIR_Entry[0] = ((entry->RTAGOFFSET_0 & 0x1) << 0)

  | ((entry->RTAGOFFSET_1 & 0x1) << 1)

  | ((entry->RTAGOFFSET_2 & 0x1) << 2)

  | ((entry->RTAGOFFSET_3 & 0x1) << 3)

  | ((entry->RTAGOFFSET_4 & 0x1) << 4)

  | ((entry->RTAGOFFSET_5 & 0x1) << 5)

  | ((entry->RTAGOFFSET_6 & 0x1) << 6)

  | ((entry->RTAGOFFSET_7 & 0x1) << 7)

  | ((entry->RTAGOFFSET_8 & 0x1) <<

  | ((entry->RTAGOFFSET_9 & 0x1) << 9)

  | ((entry->RTAGOFFSET_10 & 0x1) << 10);

    Write_SGIR_Entry[1] = ((entry->REPLACE_PORTS & 0xFFFF) << 0)

  | ((entry->TAG_PORTS & 0xFFFF) << 16);

    Write_SGIR_Entry[2] = ((entry->IND_REC_PORTS & 0xFFFF) << 0)

  | ((entry->SEQ_REC_PORTS & 0xFFFF) << 16);

    Write_SGIR_Entry[3] = ((entry->IND_REC_TIMEOUT & 0xFFFF) << 0)

  | ((entry->SEQRECOFFSET & 0xFFFF) << 16);

    Write_SGIR_Entry[4] = ((entry->GENSEQNUM & 0xFFFF) << 0)

  | ((entry->tstled & 0x1) << 16)

  | ((entry->rstled & 0x1) << 17)

  | ((entry->seqgenrst & 0x1) << 18);

}

void write_SGIR(const CB_SGIR_Entry* entry) {

uint32_t SWREG_BASE = 0x00000000;

uint32_t CB_SGIR_OFFSET = 0xFF000238;

uint32_t CB_SGIR_CTRL_OFFSET = 0xFF00024C;

uint32_t VALID = (1U << 31);

uint32_t RDWRSET = (1U << 30);

uint32_t TARGETEDTBL = (0U << 6);

uint32_t ADDR_RANGE = 5;

uint32_t TABLE_SIZE = 64;

volatile uint32_t* const CB_SGIR_TABLE = (uint32_t*)(SWREG_BASE + CB_SGIR_OFFSET);

volatile uint32_t* const CB_SGIR_CTRL  = (uint32_t*)(SWREG_BASE + CB_SGIR_CTRL_OFFSET);

uint32_t Write_SGIR_Entry[ADDR_RANGE];

SGIR_Entry(entry, Write_SGIR_Entry);

uint32_t control_word = VALID | RDWRSET | (TARGETEDTBL) | (entry->index & 0x3F);

for (int i = 0; i < ADDR_RANGE; i++) {

CB_SGIR_TABLE[i] = Write_SGIR_Entry[i];

}

*CB_SGIR_CTRL = control_word;

}

void ConfigSGIR(uint8_t index,uint16_t tag_ports,uint16_t replace_ports,uint16_t ind_rec_ports,uint16_t seq_rec_ports,

uint16_t ind_rec_timeout,uint16_t seqrec_offset,uint16_t genseqnum,uint8_t seqgenrst,uint8_t tstled,uint8_t rstled,

uint8_t rtagoffset[11]) {

    CB_SGIR_Entry entry = {0};

    entry.index = index;

    entry.TAG_PORTS = tag_ports;

    entry.REPLACE_PORTS = replace_ports;

    entry.IND_REC_PORTS = ind_rec_ports;

    entry.SEQ_REC_PORTS = seq_rec_ports;

    entry.IND_REC_TIMEOUT = ind_rec_timeout;

    entry.SEQRECOFFSET = seqrec_offset;

    entry.GENSEQNUM = genseqnum;

    entry.seqgenrst = seqgenrst;

    entry.tstled = tstled;

    entry.rstled = rstled;

    entry.RTAGOFFSET_0 = rtagoffset[0];

    entry.RTAGOFFSET_1 = rtagoffset[1];

    entry.RTAGOFFSET_2 = rtagoffset[2];

    entry.RTAGOFFSET_3 = rtagoffset[3];

    entry.RTAGOFFSET_4 = rtagoffset[4];

    entry.RTAGOFFSET_5 = rtagoffset[5];

    entry.RTAGOFFSET_6 = rtagoffset[6];

    entry.RTAGOFFSET_7 = rtagoffset[7];

    entry.RTAGOFFSET_8 = rtagoffset[8];

    entry.RTAGOFFSET_9 = rtagoffset[9];

    entry.RTAGOFFSET_10 = rtagoffset[10];

    write_SGIR(&entry);

}

int main(){
ConfigSGIR(0, (1 << 1) | (1 << 2), 0, 0, 0, 0, 0, 1, 0, 0, 0, rtagoffsets0);
}
whether this code is correct to execute for Creating a Dynamic Entry ??

[PavelL]

Hello @Atkinson ,

creating and evaluating such a script falls outside the scope of our complimentary support.

Thank you for your understanding.

Best regards,

Pavel

[Atkinson]

Hi @PavelL 

The below script is the example script which created for Dynamically creating a Entry which operates for L2 Lookup table by Index 

int WriteCB_SG_IR(){

uint32_t CBSGIR_OFFSET     = 0xFF000238;

uint32_t CBSGIR_CTRL_OFFSET = 0xFF00024C;

const uint32_t SWREG_BASE    = 0x00000000;

volatile uint32_t* CB_SG_IR_ADDRESS      = (uint32_t*)(SWREG_BASE + CBSGIR_OFFSET);

volatile uint32_t* CB_SG_IR_ADDRESS_CTL  = (uint32_t*)(SWREG_BASE + CBSGIR_CTRL_OFFSET);

uint32_t RTAGOFFSET_10 = 0;

uint32_t RTAGOFFSET_9 = 0;

uint32_t RTAGOFFSET_8 = 0;

uint32_t RTAGOFFSET_7 = 0;

uint32_t RTAGOFFSET_6 = 0;

uint32_t RTAGOFFSET_5 = 0;

uint32_t RTAGOFFSET_4 = 0;

uint32_t RTAGOFFSET_3 = 0;

uint32_t RTAGOFFSET_2 = 0;

uint32_t RTAGOFFSET_1 = 0;

uint32_t RTAGOFFSET_0 = 0;

uint32_t REPLACE_PORTS = 0;

uint32_t TAG_PORTS = 0x006;

uint32_t SEQ_REC_PORTS = 0;

uint32_t IND_REC_PORTS = 0;

uint32_t IND_REC_TIMEOUT = 0;

uint32_t SEQRECOFFSET = 0;

uint32_t GENSEQNUM = 1;

uint32_t INDEX = 0;

uint32_t SEQGENRST = 0;

uint32_t VALID = 1U;

uint32_t RDWRSET = 1U ;

uint32_t TARGETEDTBL = 0U;

uint32_t TABLE_SIZE = 64;

uint32_t CB_SG_IR_Entry[CB_SGIR_ADDR_RANGE] = {0};

CB_SG_IR_Entry[0] =

    ((GENSEQNUM & 0x1) << 1) |

    ((SEQRECOFFSET & 0x1F) << 2) |

    ((IND_REC_TIMEOUT & 0xFFFF) << 7);

CB_SG_IR_Entry[1] =

    ((SEQ_REC_PORTS & 0x7FF) << 0) |

    ((IND_REC_PORTS & 0x7FF) << 11);

CB_SG_IR_Entry[2] =

    ((TAG_PORTS & 0x7FF) << 0) |

    ((REPLACE_PORTS & 0x7FF) << 11);

CB_SG_IR_Entry[3] =

    ((RTAGOFFSET_0 & 0x3F) << 0)  |

    ((RTAGOFFSET_1 & 0x3F) << 6)  |

    ((RTAGOFFSET_2 & 0x3F) << 12) |

    ((RTAGOFFSET_3 & 0x3F) << 18) |

    ((RTAGOFFSET_4 & 0x3F) << 24);

CB_SG_IR_Entry[4] =

    ((RTAGOFFSET_5 & 0x3F) << 0)  |

    ((RTAGOFFSET_6 & 0x3F) << 6)  |

    ((RTAGOFFSET_7 & 0x3F) << 12) |

    ((RTAGOFFSET_8 & 0x3F) << 18) |

    ((RTAGOFFSET_9 & 0x3F) << 24) |

    ((RTAGOFFSET_10 & 0x3F) << 30);

uint32_t status = *CB_SG_IR_ADDRESS_CTL;

while ((status & (1U << 31)) != 0) {

status = *CB_SG_IR_ADDRESS_CTL;

}

for (int i = 0; i < CB_SGIR_ADDR_RANGE; i++) {

CB_SG_IR_ADDRESS[i] = CB_SG_IR_Entry[i];

    if (CB_SG_IR_ADDRESS[i] != CB_SG_IR_Entry[i]) {

         return -3;

    }

}

uint32_t CTRL_VALUE = ((VALID << 31) + (RDWRSET << 30) + (SEQGENRST << 9) + (TARGETEDTBL << 6) + (INDEX & 0b111111));

*CB_SG_IR_ADDRESS_CTL = CTRL_VALUE;

do {

status = *CB_SG_IR_ADDRESS_CTL;

} while ((status >> 31) & 1U);

return 0;

}

I am having a certain questions ??
The above script which i provided is same as write_le_lookup_table.py with change in address and Control Address which i created it ? so in order to create a dynamic Entry we can replicate as same as that ryt ??
whether it will work that was the sample code above is provided because in cb_sg_ir.py is completely differ from write_l2_lookup_table.py ?

whether index value also need to be encoded into the CB_SG_IR_Entry[] ??
so whether any order need to be maintained CB_SG_IR_Entry[0],[1],[2],[3]
because inside values need to be maintained in certain order 

In TAG_PORTS = 0x006 which i gave in that TAG_PORTS = port 1 & Port 2 whether that is correct ??

[Atkinson]

Hi @PavelL 

Whether the address for Creating a dynamic Entry which i used is correct or different address need to be used 

[PavelL]

Hello @Atkinson ,

The principle for dynamically creating entries in the CB Sequence Generation / Individual Recovery Table (CB_SG_IR) is similar to the approach used for dynamic entries in the L2 Lookup Table, such as in write_l2_lookup_table.py. However, there are important differences in the table layout, control register configuration, and number of words per entry.

Q1: The above script which I provided is same as write_l2_lookup_table.py with change in address and Control Address which I created it? So in order to create a dynamic Entry we can replicate as same as that right?

Yes, the concept is similar. You can replicate the dynamic entry creation logic from write_l2_lookup_table.py, but you must adapt it to the CB_SG_IR table specifics:

• Use the correct base and control offsets (CBSGIR_OFFSET, CBSGIR_CTRL_OFFSET)

• Ensure the entry format matches the CB_SG_IR layout (5 words)

• Set TARGETEDTBL = 0 for CB_SG_IR (unlike L2 which uses TARGETEDTBL = 1)

• Use the appropriate control word format including VALID, RDWRSET, SEQGENRST, and INDEX

The Python script cb_sg_ir.py implements this logic correctly using the CB_SGIR_Entry and CB_SGIR_Table classes.

Q2: Whether index value also need to be encoded into the CB_SG_IR_Entry[]?

No, the index is not encoded into the CB_SG_IR_Entry[] data array. It is only used in the control word written to the control register (CB_SG_IR_ADDRESS_CTL), which triggers the hardware to apply the entry at the specified index.

Q3: So whether any order need to be maintained CB_SG_IR_Entry[0],[1],[2],[3] because inside values need to be maintained in certain order?

Yes, the order of words in CB_SG_IR_Entry[] must be strictly maintained. Each word corresponds to a specific part of the hardware table entry as defined in the layout. The Python script cb_sg_ir.py handles this ordering automatically based on the layout definition.

Q4: In TAG_PORTS = 0x006 which I gave in that TAG_PORTS = port 1 & Port 2 whether that is correct?

Yes, that is correct. The value 0x006 in binary is 0000 0000 0110, which sets bits 1 and 2 - corresponding to port 1 and port 2. This matches the expected encoding for port selection.

Bets regards,

Pavel

[Atkinson]

Hi @PavelL 

Thanks for the response.

The code which i provided is the modified and applicable version. Of CB Sequence Generation and Recovery Table so I maintained a standard which it requires to create a dynamic entry.

Ca. You just confirm whether it is correct to create a Dynamci entry for CB Sequence Generation and Recovery Table.

I am having a doubt in the case of entry[0][1][2][3][4] so acne you provide me the exact version of order which will help us to create a dynamic entry.

And one more thing cb_sg_ir.py file there is not order for creating a entry its like a parsing of data getentry, setentry can you confirm me the order of array which I have created to make a dynamic entry 

[PavelL]

Hello @Atkinson ,

Yes, your code for dynamically creating an entry in the CB Sequence Generation and Individual Recovery Table (CB_SG_IR) is valid. This conclusion is based on the official Python implementation (cb_sg_ir.py) provided by NXP, which uses the same layout and logic for dynamic configuration.

Your Question:
"I am having a doubt in the case of entry[0][1][2][3][4] so can you provide me the exact version of order which will help us to create a dynamic entry?"

Yes — the order of the 5 words in the CB_SG_IR_Entry[] array is important and must follow the bit layout defined in the hardware specification (Table 1148). Based on that, the correct mapping is:

Word Index	Bit Range	Fields Included
entry[4]	159–124	RTAGOFFSET_10 to RTAGOFFSET_5
entry[3]	123–94	RTAGOFFSET_4 to RTAGOFFSET_0
entry[2]	93–72	REPLACE_PORTS, TAG_PORTS
entry[1]	71–50	IND_REC_PORTS, SEQ_REC_PORTS
entry[0]	49–28	IND_REC_TIMEOUT, SEQRECOFFSET, GENSEQNUM

Bits 27–0 are reserved and unused.

This matches the layout used internally in the Python script and confirms that your manual construction of the entry array is correct.

Your Question:
"And one more thing cb_sg_ir.py file there is not order for creating a entry its like a parsing of data getentry, setentry can you confirm me the order of array which I have created to make a dynamic entry?"

Correct — the Python script uses a layout-based approach to automatically pack and unpack the fields into the correct word order. While the script does not explicitly show the word array, it enforces the correct order internally. Your C implementation, which manually constructs the 5-word array, is consistent with this logic and is valid.

Best regards,

Pavel